{"title":"基于重试的同步在线测试相同逻辑块","authors":"Irith Pomeranz","doi":"10.1109/TVLSI.2024.3501402","DOIUrl":null,"url":null,"abstract":"State-of-the-art designs include identical instances of logic blocks to support parallel computations. Identical logic blocks at close physical proximity can be tested online by comparing their output sequences. This removes the need for known input and output sequences. To use output comparison for two logic blocks, <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula>, the logic blocks should be synchronized to the same state, and the same input sequence should be applied to them. Assuming that <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula> performs functional computations and <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula> is idle, a process described earlier synchronizes <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula> to the state of <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula> by using a synchronization period where <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula> receives the input sequence of <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula>, and values of selected state variables are copied from <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula>. A single synchronization period was used earlier. The first key contribution of this article is to introduce a retry-based synchronization process with multiple synchronization periods to avoid flagging synchronization failures as faults. The second contribution of this article is to develop the synchronization process in a simulation environment that considers functional operation conditions. Experimental results for benchmark circuits demonstrate the effectiveness of the retry-based process and the importance of the functional simulation environment.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1447-1451"},"PeriodicalIF":2.8000,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Retry-Based Synchronization for Online Testing of Identical Logic Blocks\",\"authors\":\"Irith Pomeranz\",\"doi\":\"10.1109/TVLSI.2024.3501402\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"State-of-the-art designs include identical instances of logic blocks to support parallel computations. Identical logic blocks at close physical proximity can be tested online by comparing their output sequences. This removes the need for known input and output sequences. To use output comparison for two logic blocks, <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula>, the logic blocks should be synchronized to the same state, and the same input sequence should be applied to them. Assuming that <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula> performs functional computations and <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula> is idle, a process described earlier synchronizes <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula> to the state of <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula> by using a synchronization period where <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula> receives the input sequence of <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula>, and values of selected state variables are copied from <inline-formula> <tex-math>$B_{0}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$B_{1}$ </tex-math></inline-formula>. A single synchronization period was used earlier. The first key contribution of this article is to introduce a retry-based synchronization process with multiple synchronization periods to avoid flagging synchronization failures as faults. The second contribution of this article is to develop the synchronization process in a simulation environment that considers functional operation conditions. Experimental results for benchmark circuits demonstrate the effectiveness of the retry-based process and the importance of the functional simulation environment.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":\"33 5\",\"pages\":\"1447-1451\"},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-11-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10767426/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10767426/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Retry-Based Synchronization for Online Testing of Identical Logic Blocks
State-of-the-art designs include identical instances of logic blocks to support parallel computations. Identical logic blocks at close physical proximity can be tested online by comparing their output sequences. This removes the need for known input and output sequences. To use output comparison for two logic blocks, $B_{0}$ and $B_{1}$ , the logic blocks should be synchronized to the same state, and the same input sequence should be applied to them. Assuming that $B_{0}$ performs functional computations and $B_{1}$ is idle, a process described earlier synchronizes $B_{1}$ to the state of $B_{0}$ by using a synchronization period where $B_{1}$ receives the input sequence of $B_{0}$ , and values of selected state variables are copied from $B_{0}$ to $B_{1}$ . A single synchronization period was used earlier. The first key contribution of this article is to introduce a retry-based synchronization process with multiple synchronization periods to avoid flagging synchronization failures as faults. The second contribution of this article is to develop the synchronization process in a simulation environment that considers functional operation conditions. Experimental results for benchmark circuits demonstrate the effectiveness of the retry-based process and the importance of the functional simulation environment.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.