基于重试的同步在线测试相同逻辑块

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Irith Pomeranz
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引用次数: 0

摘要

最先进的设计包括相同的逻辑块实例来支持并行计算。物理上接近的相同逻辑块可以通过比较它们的输出序列来在线测试。这样就不需要已知的输入和输出序列。为了对两个逻辑块$B_{0}$和$B_{1}$使用输出比较,逻辑块应该同步到相同的状态,并且应该对它们应用相同的输入序列。假设$B_{0}$执行函数式计算,而$B_{1}$处于空闲状态,那么前面描述的进程将使用一个同步周期将$B_{1}$同步到$B_{0}$状态,其中$B_{1}$接收$B_{0}$的输入序列,并将所选状态变量的值从$B_{0}$复制到$B_{1}$。之前使用了单个同步周期。本文的第一个关键贡献是引入了一个基于重试的同步过程,该过程具有多个同步周期,以避免将同步失败标记为故障。本文的第二个贡献是在考虑功能操作条件的模拟环境中开发同步过程。基准电路的实验结果证明了基于重试的过程的有效性和功能仿真环境的重要性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Retry-Based Synchronization for Online Testing of Identical Logic Blocks
State-of-the-art designs include identical instances of logic blocks to support parallel computations. Identical logic blocks at close physical proximity can be tested online by comparing their output sequences. This removes the need for known input and output sequences. To use output comparison for two logic blocks, $B_{0}$ and $B_{1}$ , the logic blocks should be synchronized to the same state, and the same input sequence should be applied to them. Assuming that $B_{0}$ performs functional computations and $B_{1}$ is idle, a process described earlier synchronizes $B_{1}$ to the state of $B_{0}$ by using a synchronization period where $B_{1}$ receives the input sequence of $B_{0}$ , and values of selected state variables are copied from $B_{0}$ to $B_{1}$ . A single synchronization period was used earlier. The first key contribution of this article is to introduce a retry-based synchronization process with multiple synchronization periods to avoid flagging synchronization failures as faults. The second contribution of this article is to develop the synchronization process in a simulation environment that considers functional operation conditions. Experimental results for benchmark circuits demonstrate the effectiveness of the retry-based process and the importance of the functional simulation environment.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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