基于相域和电压域混合校准的 7.4-9.2-GHz 分数-N 差分采样 PLL

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-11-22 DOI:10.1109/TVLSI.2024.3496931

Feng Bu;Ruixue Ding;Depeng Sun;Ge Wang;Yuan Gao;Rong Zhou;Xiaoteng Zhao;Lisheng Chen;Shubin Liu;Zhangming Zhu

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引用次数: 0

摘要

本文提出了一种7.4 - 9.2 ghz低噪声分数n差分采样锁相环（DSPLL），具有双相位检测器（PD）增益。采用相域和电压域混合校准，补偿了δ - σ调制器（DSM）的累积量化误差（Q-error），解决了采样电压波动大引起的锁定问题。同时，引入移压技术对差分采样PD （DSPD）的锁定电压区进行调整，提高了DSPLL的线性度，从而达到更好的校准效果。该DSPLL采用65纳米CMOS工艺制造，在整数n和分数n模式下的测量积分抖动分别为69.09和73.26 fs。参考杂散为−72.96 dBc，最差分数杂散为−55.26 dBc。在1.2 v电源下，总功耗为19.2 mW，性能抖动值（FOMJ）为−249.9 dB。

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A 7.4–9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration

This brief proposes a 7.4–9.2-GHz low-noise fractional-N differential sampling phase-locked loop (DSPLL), which features doubled phase detector (PD) gain. By using the phase-domain and voltage-domain hybrid calibration, the accumulated quantization error (Q-error) of the delta-sigma modulator (DSM) is compensated, and the locking problem caused by large sampling voltage fluctuation is solved. Meanwhile, a voltage shifting technique is introduced to adjust the locked voltage region of differential sampling PD (DSPD), which can improve the linearity of DSPLL for better calibration. Fabricated in 65-nm CMOS process, the presented DSPLL achieves measured integrated jitter of 69.09 and 73.26 fs for integer-N and fractional-N modes, respectively. The reference spur is −72.96 dBc, and the worst fractional spur is −55.26 dBc. The total power consumption is 19.2 mW at a 1.2-V supply, achieving a figure of merit jitter (FOMJ) of −249.9 dB.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.