修正“使用数字杂散抵消的<90-fs抖动和<-103-dBc杂散音的分数频率合成器的设计和分析”

IF 4.6 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of Solid-state Circuits Pub Date : 2025-04-24 DOI:10.1109/JSSC.2025.3550254

Mohammadreza Zeinali;Sudhakar Pamarti

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引用次数: 0

摘要

本文对我们之前发表的手稿中的一处错误进行了更正。更正涉及主要分数频率合成器结构及其相关组件的传递函数表示。此外，根座分析也需要根据这一更正进行修改。这些修改并不影响结果的整体有效性，原文的主要结论保持不变。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”

This article provides a correction to an error in our previously published manuscript. The correction pertains to the transfer function representation of the main fractional frequency synthesizer structure and its associated components. In addition, the root locus analysis requires revision based on this correction. These modifications do not affect the overall validity of the results, and the main conclusions of the original article remain unchanged.

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来源期刊

IEEE Journal of Solid-state Circuits 工程技术-工程：电子与电气

CiteScore

11.00

自引率

20.40%

发文量

351

审稿时长

3-6 weeks

期刊介绍： The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.