{"title":"全桥单相整流结构级联h桥逆变器容错调制技术的改进","authors":"Kasra Khalili, Jalal Nazarzadeh","doi":"10.1049/pel2.70040","DOIUrl":null,"url":null,"abstract":"<p>This paper presents a novel fault-tolerant approach for cascaded H-bridge inverters with a full-bridge single-phase rectifier cell structure. Upon a fault, the faulty cell is disconnected from the circuit, and the inverter switches from normal operation (symmetric mode) to faulted operation (asymmetric mode). In asymmetric mode, one of the full-bridge single-phase rectifier cells in the faulty phase transitions from a full-bridge to a half-bridge configuration. The level-shift pulse-width modulation (PWM) is employed during symmetric mode, while a modified level-shift PWM is utilized in asymmetric mode. The inverter's output power and voltage remain unchanged during faults in the modified PWM method. Additionally, the performance of the proposed fault-tolerant algorithm is evaluated and validated using results from simulations and an experimental prototype of a seven-level inverter.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7000,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70040","citationCount":"0","resultStr":"{\"title\":\"Improved Modulation Technique in Cascaded H-Bridge Inverters for Fault-Tolerant With Full Bridge Single Phase Rectifier Structure\",\"authors\":\"Kasra Khalili, Jalal Nazarzadeh\",\"doi\":\"10.1049/pel2.70040\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>This paper presents a novel fault-tolerant approach for cascaded H-bridge inverters with a full-bridge single-phase rectifier cell structure. Upon a fault, the faulty cell is disconnected from the circuit, and the inverter switches from normal operation (symmetric mode) to faulted operation (asymmetric mode). In asymmetric mode, one of the full-bridge single-phase rectifier cells in the faulty phase transitions from a full-bridge to a half-bridge configuration. The level-shift pulse-width modulation (PWM) is employed during symmetric mode, while a modified level-shift PWM is utilized in asymmetric mode. The inverter's output power and voltage remain unchanged during faults in the modified PWM method. Additionally, the performance of the proposed fault-tolerant algorithm is evaluated and validated using results from simulations and an experimental prototype of a seven-level inverter.</p>\",\"PeriodicalId\":56302,\"journal\":{\"name\":\"IET Power Electronics\",\"volume\":\"18 1\",\"pages\":\"\"},\"PeriodicalIF\":1.7000,\"publicationDate\":\"2025-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70040\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IET Power Electronics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1049/pel2.70040\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Power Electronics","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/pel2.70040","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Improved Modulation Technique in Cascaded H-Bridge Inverters for Fault-Tolerant With Full Bridge Single Phase Rectifier Structure
This paper presents a novel fault-tolerant approach for cascaded H-bridge inverters with a full-bridge single-phase rectifier cell structure. Upon a fault, the faulty cell is disconnected from the circuit, and the inverter switches from normal operation (symmetric mode) to faulted operation (asymmetric mode). In asymmetric mode, one of the full-bridge single-phase rectifier cells in the faulty phase transitions from a full-bridge to a half-bridge configuration. The level-shift pulse-width modulation (PWM) is employed during symmetric mode, while a modified level-shift PWM is utilized in asymmetric mode. The inverter's output power and voltage remain unchanged during faults in the modified PWM method. Additionally, the performance of the proposed fault-tolerant algorithm is evaluated and validated using results from simulations and an experimental prototype of a seven-level inverter.
期刊介绍:
IET Power Electronics aims to attract original research papers, short communications, review articles and power electronics related educational studies. The scope covers applications and technologies in the field of power electronics with special focus on cost-effective, efficient, power dense, environmental friendly and robust solutions, which includes:
Applications:
Electric drives/generators, renewable energy, industrial and consumable applications (including lighting, welding, heating, sub-sea applications, drilling and others), medical and military apparatus, utility applications, transport and space application, energy harvesting, telecommunications, energy storage management systems, home appliances.
Technologies:
Circuits: all type of converter topologies for low and high power applications including but not limited to: inverter, rectifier, dc/dc converter, power supplies, UPS, ac/ac converter, resonant converter, high frequency converter, hybrid converter, multilevel converter, power factor correction circuits and other advanced topologies.
Components and Materials: switching devices and their control, inductors, sensors, transformers, capacitors, resistors, thermal management, filters, fuses and protection elements and other novel low-cost efficient components/materials.
Control: techniques for controlling, analysing, modelling and/or simulation of power electronics circuits and complete power electronics systems.
Design/Manufacturing/Testing: new multi-domain modelling, assembling and packaging technologies, advanced testing techniques.
Environmental Impact: Electromagnetic Interference (EMI) reduction techniques, Electromagnetic Compatibility (EMC), limiting acoustic noise and vibration, recycling techniques, use of non-rare material.
Education: teaching methods, programme and course design, use of technology in power electronics teaching, virtual laboratory and e-learning and fields within the scope of interest.
Special Issues. Current Call for papers:
Harmonic Mitigation Techniques and Grid Robustness in Power Electronic-Based Power Systems - https://digital-library.theiet.org/files/IET_PEL_CFP_HMTGRPEPS.pdf