Jiahao Cai;Hamza E. Barkam;Mohsen Imani;Kai Ni;Grace Li Zhang;Bing Li;Ulf Schlichtmann;Cheng Zhuo;Xunzhao Yin
{"title":"基于2t - 1fet的可扩展内容寻址存储器节能数据搜索设计","authors":"Jiahao Cai;Hamza E. Barkam;Mohsen Imani;Kai Ni;Grace Li Zhang;Bing Li;Ulf Schlichtmann;Cheng Zhuo;Xunzhao Yin","doi":"10.1109/TCAD.2024.3493000","DOIUrl":null,"url":null,"abstract":"Content addressable memory (CAM) is widely used in advanced machine learning models and data-intensive applications for associative search tasks, thanks to the highly parallel pattern matching capability. Most state-of-the-art CAM designs primarily aim to reduce the CAM cell area by utilizing nonvolatile memories (NVMs). However, there has been limited research on optimizing the design and energy efficiency of NVM-based CAMs for practical deployment in edge devices and AI hardware. This article introduces a general compact and energy efficient CAM design scheme that minimizes design overhead by using only one NVM device per cell. Our proposed CAM design realizes both binary CAM (BCAM) and multibit CAM (MCAM) by leveraging the binary and multilevel storage property of NVM devices without additional cell overheads. Additionally, we propose an adaptive matchline (ML) precharge and discharge scheme to further optimize search energy by significantly reducing the ML voltage swing. Ferroelectric field-effect transistors (FeFETs) serve as representative NVMs in our proposed design, and we present a 2T-1FeFET CAM array incorporating a sense amplifier that implements the proposed ML scheme. Evaluation results show that our proposed 2T-1FeFET BCAM design achieves energy efficiency improvements of <inline-formula> <tex-math>$6.64\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$4.74\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$9.14\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$3.02\\times $ </tex-math></inline-formula> compared to CMOS/ReRAM/STT-MRAM/2FeFET BCAM arrays, while 2T-1FeFET MCAM design achieves <inline-formula> <tex-math>$8.25\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$5.68\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$56.35\\times $ </tex-math></inline-formula> better-energy efficiency compared to ReRAM/3T-1FeFET/1FeFET-1R MACM arrays. Benchmarking results demonstrate that our BCAM/MCAM approach provides <inline-formula> <tex-math>$3.2\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$3.7\\times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.0\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$2.2\\times $ </tex-math></inline-formula> energy-delay product improvement over the 2T-2R and 2FeFET CAM in accelerating query processing applications.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1760-1773"},"PeriodicalIF":2.7000,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search\",\"authors\":\"Jiahao Cai;Hamza E. Barkam;Mohsen Imani;Kai Ni;Grace Li Zhang;Bing Li;Ulf Schlichtmann;Cheng Zhuo;Xunzhao Yin\",\"doi\":\"10.1109/TCAD.2024.3493000\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Content addressable memory (CAM) is widely used in advanced machine learning models and data-intensive applications for associative search tasks, thanks to the highly parallel pattern matching capability. Most state-of-the-art CAM designs primarily aim to reduce the CAM cell area by utilizing nonvolatile memories (NVMs). However, there has been limited research on optimizing the design and energy efficiency of NVM-based CAMs for practical deployment in edge devices and AI hardware. This article introduces a general compact and energy efficient CAM design scheme that minimizes design overhead by using only one NVM device per cell. Our proposed CAM design realizes both binary CAM (BCAM) and multibit CAM (MCAM) by leveraging the binary and multilevel storage property of NVM devices without additional cell overheads. Additionally, we propose an adaptive matchline (ML) precharge and discharge scheme to further optimize search energy by significantly reducing the ML voltage swing. Ferroelectric field-effect transistors (FeFETs) serve as representative NVMs in our proposed design, and we present a 2T-1FeFET CAM array incorporating a sense amplifier that implements the proposed ML scheme. Evaluation results show that our proposed 2T-1FeFET BCAM design achieves energy efficiency improvements of <inline-formula> <tex-math>$6.64\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$4.74\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$9.14\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$3.02\\\\times $ </tex-math></inline-formula> compared to CMOS/ReRAM/STT-MRAM/2FeFET BCAM arrays, while 2T-1FeFET MCAM design achieves <inline-formula> <tex-math>$8.25\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$5.68\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$56.35\\\\times $ </tex-math></inline-formula> better-energy efficiency compared to ReRAM/3T-1FeFET/1FeFET-1R MACM arrays. Benchmarking results demonstrate that our BCAM/MCAM approach provides <inline-formula> <tex-math>$3.2\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$3.7\\\\times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.0\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$2.2\\\\times $ </tex-math></inline-formula> energy-delay product improvement over the 2T-2R and 2FeFET CAM in accelerating query processing applications.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"44 5\",\"pages\":\"1760-1773\"},\"PeriodicalIF\":2.7000,\"publicationDate\":\"2024-11-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10745585/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10745585/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search
Content addressable memory (CAM) is widely used in advanced machine learning models and data-intensive applications for associative search tasks, thanks to the highly parallel pattern matching capability. Most state-of-the-art CAM designs primarily aim to reduce the CAM cell area by utilizing nonvolatile memories (NVMs). However, there has been limited research on optimizing the design and energy efficiency of NVM-based CAMs for practical deployment in edge devices and AI hardware. This article introduces a general compact and energy efficient CAM design scheme that minimizes design overhead by using only one NVM device per cell. Our proposed CAM design realizes both binary CAM (BCAM) and multibit CAM (MCAM) by leveraging the binary and multilevel storage property of NVM devices without additional cell overheads. Additionally, we propose an adaptive matchline (ML) precharge and discharge scheme to further optimize search energy by significantly reducing the ML voltage swing. Ferroelectric field-effect transistors (FeFETs) serve as representative NVMs in our proposed design, and we present a 2T-1FeFET CAM array incorporating a sense amplifier that implements the proposed ML scheme. Evaluation results show that our proposed 2T-1FeFET BCAM design achieves energy efficiency improvements of $6.64\times $ /$4.74\times $ /$9.14\times $ /$3.02\times $ compared to CMOS/ReRAM/STT-MRAM/2FeFET BCAM arrays, while 2T-1FeFET MCAM design achieves $8.25\times $ /$5.68\times $ /$56.35\times $ better-energy efficiency compared to ReRAM/3T-1FeFET/1FeFET-1R MACM arrays. Benchmarking results demonstrate that our BCAM/MCAM approach provides $3.2\times $ /$3.7\times $ and $2.0\times $ /$2.2\times $ energy-delay product improvement over the 2T-2R and 2FeFET CAM in accelerating query processing applications.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.