基于2t - 1fet的可扩展内容寻址存储器节能数据搜索设计

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jiahao Cai;Hamza E. Barkam;Mohsen Imani;Kai Ni;Grace Li Zhang;Bing Li;Ulf Schlichtmann;Cheng Zhuo;Xunzhao Yin
{"title":"基于2t - 1fet的可扩展内容寻址存储器节能数据搜索设计","authors":"Jiahao Cai;Hamza E. Barkam;Mohsen Imani;Kai Ni;Grace Li Zhang;Bing Li;Ulf Schlichtmann;Cheng Zhuo;Xunzhao Yin","doi":"10.1109/TCAD.2024.3493000","DOIUrl":null,"url":null,"abstract":"Content addressable memory (CAM) is widely used in advanced machine learning models and data-intensive applications for associative search tasks, thanks to the highly parallel pattern matching capability. Most state-of-the-art CAM designs primarily aim to reduce the CAM cell area by utilizing nonvolatile memories (NVMs). However, there has been limited research on optimizing the design and energy efficiency of NVM-based CAMs for practical deployment in edge devices and AI hardware. This article introduces a general compact and energy efficient CAM design scheme that minimizes design overhead by using only one NVM device per cell. Our proposed CAM design realizes both binary CAM (BCAM) and multibit CAM (MCAM) by leveraging the binary and multilevel storage property of NVM devices without additional cell overheads. Additionally, we propose an adaptive matchline (ML) precharge and discharge scheme to further optimize search energy by significantly reducing the ML voltage swing. Ferroelectric field-effect transistors (FeFETs) serve as representative NVMs in our proposed design, and we present a 2T-1FeFET CAM array incorporating a sense amplifier that implements the proposed ML scheme. Evaluation results show that our proposed 2T-1FeFET BCAM design achieves energy efficiency improvements of <inline-formula> <tex-math>$6.64\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$4.74\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$9.14\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$3.02\\times $ </tex-math></inline-formula> compared to CMOS/ReRAM/STT-MRAM/2FeFET BCAM arrays, while 2T-1FeFET MCAM design achieves <inline-formula> <tex-math>$8.25\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$5.68\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$56.35\\times $ </tex-math></inline-formula> better-energy efficiency compared to ReRAM/3T-1FeFET/1FeFET-1R MACM arrays. Benchmarking results demonstrate that our BCAM/MCAM approach provides <inline-formula> <tex-math>$3.2\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$3.7\\times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.0\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$2.2\\times $ </tex-math></inline-formula> energy-delay product improvement over the 2T-2R and 2FeFET CAM in accelerating query processing applications.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"1760-1773"},"PeriodicalIF":2.7000,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search\",\"authors\":\"Jiahao Cai;Hamza E. Barkam;Mohsen Imani;Kai Ni;Grace Li Zhang;Bing Li;Ulf Schlichtmann;Cheng Zhuo;Xunzhao Yin\",\"doi\":\"10.1109/TCAD.2024.3493000\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Content addressable memory (CAM) is widely used in advanced machine learning models and data-intensive applications for associative search tasks, thanks to the highly parallel pattern matching capability. Most state-of-the-art CAM designs primarily aim to reduce the CAM cell area by utilizing nonvolatile memories (NVMs). However, there has been limited research on optimizing the design and energy efficiency of NVM-based CAMs for practical deployment in edge devices and AI hardware. This article introduces a general compact and energy efficient CAM design scheme that minimizes design overhead by using only one NVM device per cell. Our proposed CAM design realizes both binary CAM (BCAM) and multibit CAM (MCAM) by leveraging the binary and multilevel storage property of NVM devices without additional cell overheads. Additionally, we propose an adaptive matchline (ML) precharge and discharge scheme to further optimize search energy by significantly reducing the ML voltage swing. Ferroelectric field-effect transistors (FeFETs) serve as representative NVMs in our proposed design, and we present a 2T-1FeFET CAM array incorporating a sense amplifier that implements the proposed ML scheme. Evaluation results show that our proposed 2T-1FeFET BCAM design achieves energy efficiency improvements of <inline-formula> <tex-math>$6.64\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$4.74\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$9.14\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$3.02\\\\times $ </tex-math></inline-formula> compared to CMOS/ReRAM/STT-MRAM/2FeFET BCAM arrays, while 2T-1FeFET MCAM design achieves <inline-formula> <tex-math>$8.25\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$5.68\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$56.35\\\\times $ </tex-math></inline-formula> better-energy efficiency compared to ReRAM/3T-1FeFET/1FeFET-1R MACM arrays. Benchmarking results demonstrate that our BCAM/MCAM approach provides <inline-formula> <tex-math>$3.2\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$3.7\\\\times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.0\\\\times $ </tex-math></inline-formula>/<inline-formula> <tex-math>$2.2\\\\times $ </tex-math></inline-formula> energy-delay product improvement over the 2T-2R and 2FeFET CAM in accelerating query processing applications.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"44 5\",\"pages\":\"1760-1773\"},\"PeriodicalIF\":2.7000,\"publicationDate\":\"2024-11-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10745585/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10745585/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

内容寻址存储器(CAM)由于其高度并行的模式匹配能力,在高级机器学习模型和数据密集型应用中广泛应用于关联搜索任务。大多数最先进的CAM设计主要旨在通过使用非易失性存储器(nvm)来减少CAM单元面积。然而,在优化基于nvm的cam的设计和能效以用于边缘设备和人工智能硬件的实际部署方面,研究有限。本文介绍了一种通用的紧凑且节能的CAM设计方案,该方案通过每个单元仅使用一个NVM设备来最小化设计开销。我们提出的CAM设计通过利用NVM设备的二进制和多级存储特性来实现二进制CAM (BCAM)和多位CAM (MCAM),而无需额外的单元开销。此外,我们提出了一种自适应匹配线(ML)预充放电方案,通过显著降低ML电压摆动来进一步优化搜索能量。在我们提出的设计中,铁电场效应晶体管(fefet)作为具有代表性的nvm,我们提出了一个2T-1FeFET CAM阵列,该阵列包含一个实现所提出的ML方案的感测放大器。评估结果表明,与CMOS/ReRAM/STT-MRAM/2FeFET BCAM阵列相比,我们提出的2T-1FeFET BCAM设计的能效提高了6.64倍/ 4.74倍/ 9.14倍/ 3.02倍,而2T-1FeFET MCAM设计的能效比ReRAM/3T-1FeFET/1FeFET-1R MACM阵列提高了8.25倍/ 5.68倍/ 56.35倍。基准测试结果表明,与2T-2R和2FeFET CAM相比,我们的BCAM/MCAM方法在加速查询处理应用方面提供了3.2\倍/ 3.7\倍和2.0\倍/ 2.2\倍的能量延迟产品改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search
Content addressable memory (CAM) is widely used in advanced machine learning models and data-intensive applications for associative search tasks, thanks to the highly parallel pattern matching capability. Most state-of-the-art CAM designs primarily aim to reduce the CAM cell area by utilizing nonvolatile memories (NVMs). However, there has been limited research on optimizing the design and energy efficiency of NVM-based CAMs for practical deployment in edge devices and AI hardware. This article introduces a general compact and energy efficient CAM design scheme that minimizes design overhead by using only one NVM device per cell. Our proposed CAM design realizes both binary CAM (BCAM) and multibit CAM (MCAM) by leveraging the binary and multilevel storage property of NVM devices without additional cell overheads. Additionally, we propose an adaptive matchline (ML) precharge and discharge scheme to further optimize search energy by significantly reducing the ML voltage swing. Ferroelectric field-effect transistors (FeFETs) serve as representative NVMs in our proposed design, and we present a 2T-1FeFET CAM array incorporating a sense amplifier that implements the proposed ML scheme. Evaluation results show that our proposed 2T-1FeFET BCAM design achieves energy efficiency improvements of $6.64\times $ / $4.74\times $ / $9.14\times $ / $3.02\times $ compared to CMOS/ReRAM/STT-MRAM/2FeFET BCAM arrays, while 2T-1FeFET MCAM design achieves $8.25\times $ / $5.68\times $ / $56.35\times $ better-energy efficiency compared to ReRAM/3T-1FeFET/1FeFET-1R MACM arrays. Benchmarking results demonstrate that our BCAM/MCAM approach provides $3.2\times $ / $3.7\times $ and $2.0\times $ / $2.2\times $ energy-delay product improvement over the 2T-2R and 2FeFET CAM in accelerating query processing applications.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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