A 20-bit 1MS/s SAR ADC suppressing the dynamic error caused by thermal effect in the static comparator

High-precision analog-to-digital converters (ADCs) play a crucial role in modern mixed-signal systems, particularly in applications demanding low noise and high resolution. This paper presents a high-precision successive approximation register (SAR) ADC implemented in a 180 nm process. A coarse SAR ADC quantizes the 8-bit most significant bits (MSBs), and a fine SAR ADC processes the remaining 12-bit least significant bits (LSBs). Both SAR ADCs simultaneously sample the input signal, and the fine ADC concurrently copies the 8-bit MSB digital code after the coarse ADC completes quantization. This approach effectively prevents large differential voltages at the comparator's input, thereby eliminating dynamic errors caused by excessive current differences in the load resistance. To further enhance performance, a four-stage pre-amplifier with output offset cancellation is employed as the comparator's pre-amplifier. Careful tuning of the pre-amplifier stages minimizes the comparator's overall bandwidth without compromising accuracy. Simulation results demonstrate an offset voltage of 13.98 μV, input-referred noise of 12.18 μV. When transient noise is enabled, FFT analysis shows a Signal-to-Noise and Distortion Ratio (SNDR) of 106.260 dB. With a power consumption of 40 mW, the Schreier figure of merit (FoM) reaches 177.2 dB, confirming the proposed ADC's suitability for high-precision applications.