PRLM: A parallel loading mechanism for a deep neural network accelerator based on NoC

Network-on-Chip (NoC) has emerged as an efficient interconnect solution for multiprocessor systems, with recent studies implementing NoC-based DNN accelerators. By interconnecting neural processing units via NoC, such designs minimize off-chip memory access, effectively reducing inference latency and power consumption. In this article, we designed the MIAO router, which supports parallel model loading and improves efficiency. It modifies traditional routers to both speed up multicast packet forwarding and optimize parallel data loading. Additionally, our path-based multicast routing minimizes redundant packets by using shared transmission paths, enhancing overall network performance. We evaluated the LeNet-5 and VGG-16 models on a simulation platform in a resource constrained NoC environment. Compared with the benchmark strategy, our solution reduces the average classification delay of the accelerator by 38.01%, packet delay by 33.16%, and packet count by 49.95%, without significantly increasing power consumption or area. This proves the superior performance of the mechanism.