{"title":"使用细胞感知测试方法的SRAM外围测试","authors":"Xhesila Xhafa;Eric Faehn;Patrick Girard;Arnaud Virazel","doi":"10.1109/TCAD.2024.3506854","DOIUrl":null,"url":null,"abstract":"Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects. This article introduces an enhanced methodology for memory testing, leveraging the cell-aware (CA) test concept. Building on prior work for SRAM array testing (Xhafa et al., 2023), we extend the CA methodology to include periphery testing by generating, for the first time, CA models for each memory input–output (I/O) element, covering key components, such as address decoders, write drivers, and sense amplifiers. We present results from testing these periphery components using the CA methodology. Additionally, we compare existing SRAM testing techniques with our CA methodology for the decoder and I/O circuitry. To ensure a fair comparison, we selected minimal March tests designed to detect functional faults in peripheral circuits, aligning with the fault models targeted by our approach. A quantitative analysis of fault coverage demonstrates the effectiveness of our methodology compared to March algorithms, particularly in terms of test complexity.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"44 5","pages":"2000-2013"},"PeriodicalIF":2.7000,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"SRAM Periphery Testing Using the Cell-Aware Test Methodology\",\"authors\":\"Xhesila Xhafa;Eric Faehn;Patrick Girard;Arnaud Virazel\",\"doi\":\"10.1109/TCAD.2024.3506854\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects. This article introduces an enhanced methodology for memory testing, leveraging the cell-aware (CA) test concept. Building on prior work for SRAM array testing (Xhafa et al., 2023), we extend the CA methodology to include periphery testing by generating, for the first time, CA models for each memory input–output (I/O) element, covering key components, such as address decoders, write drivers, and sense amplifiers. We present results from testing these periphery components using the CA methodology. Additionally, we compare existing SRAM testing techniques with our CA methodology for the decoder and I/O circuitry. To ensure a fair comparison, we selected minimal March tests designed to detect functional faults in peripheral circuits, aligning with the fault models targeted by our approach. A quantitative analysis of fault coverage demonstrates the effectiveness of our methodology compared to March algorithms, particularly in terms of test complexity.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"44 5\",\"pages\":\"2000-2013\"},\"PeriodicalIF\":2.7000,\"publicationDate\":\"2024-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10767757/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10767757/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
SRAM Periphery Testing Using the Cell-Aware Test Methodology
Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects. This article introduces an enhanced methodology for memory testing, leveraging the cell-aware (CA) test concept. Building on prior work for SRAM array testing (Xhafa et al., 2023), we extend the CA methodology to include periphery testing by generating, for the first time, CA models for each memory input–output (I/O) element, covering key components, such as address decoders, write drivers, and sense amplifiers. We present results from testing these periphery components using the CA methodology. Additionally, we compare existing SRAM testing techniques with our CA methodology for the decoder and I/O circuitry. To ensure a fair comparison, we selected minimal March tests designed to detect functional faults in peripheral circuits, aligning with the fault models targeted by our approach. A quantitative analysis of fault coverage demonstrates the effectiveness of our methodology compared to March algorithms, particularly in terms of test complexity.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.