使用细胞感知测试方法的SRAM外围测试

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Xhesila Xhafa;Eric Faehn;Patrick Girard;Arnaud Virazel
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引用次数: 0

摘要

测试存储电路对于确保片上系统(SoC)设计的质量和可靠性至关重要,特别是随着技术节点的缩小,纳米级缺陷的易感性增加。本文介绍了一种增强的内存测试方法,利用单元感知(CA)测试概念。在先前SRAM阵列测试工作的基础上(Xhafa等人,2023),我们将CA方法扩展到包括外围测试,首次为每个存储器输入输出(I/O)元素生成CA模型,涵盖关键组件,如地址解码器、写入驱动程序和感测放大器。我们展示了使用CA方法测试这些外围组件的结果。此外,我们将现有的SRAM测试技术与解码器和I/O电路的CA方法进行了比较。为了确保公平的比较,我们选择了最小的March测试,旨在检测外围电路中的功能故障,与我们的方法所针对的故障模型保持一致。与March算法相比,对故障覆盖率的定量分析证明了我们的方法的有效性,特别是在测试复杂性方面。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
SRAM Periphery Testing Using the Cell-Aware Test Methodology
Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects. This article introduces an enhanced methodology for memory testing, leveraging the cell-aware (CA) test concept. Building on prior work for SRAM array testing (Xhafa et al., 2023), we extend the CA methodology to include periphery testing by generating, for the first time, CA models for each memory input–output (I/O) element, covering key components, such as address decoders, write drivers, and sense amplifiers. We present results from testing these periphery components using the CA methodology. Additionally, we compare existing SRAM testing techniques with our CA methodology for the decoder and I/O circuitry. To ensure a fair comparison, we selected minimal March tests designed to detect functional faults in peripheral circuits, aligning with the fault models targeted by our approach. A quantitative analysis of fault coverage demonstrates the effectiveness of our methodology compared to March algorithms, particularly in terms of test complexity.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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