Xinran Yang;Yi Zhao;Lang Chen;Zeyu Ge;Jiani Zhou;Feng Sun
{"title":"增益平坦度增强的全集成GaAs MMIC非对称多尔蒂功率放大器","authors":"Xinran Yang;Yi Zhao;Lang Chen;Zeyu Ge;Jiani Zhou;Feng Sun","doi":"10.1109/LMWT.2025.3535739","DOIUrl":null,"url":null,"abstract":"A novel fully integrated asymmetric Doherty power amplifier (DPA) with optimized driver is proposed. By adjusting the unequal power divider (UPD) and the bias conditions of two-stage carrier and peak power amplifiers (PPAs), good back-off efficiency (BOE) and gain flatness have been achieved. To validate the proposed concept, a 2.45-GHz asymmetric DPA (ADPA) is fabricated in 2-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) process. Under continuous-wave (CW) measurement, the power amplifier (PA) can provide a saturated output power (<inline-formula> <tex-math>$P_{\\text {SAT}}$ </tex-math></inline-formula>) of 32.3 dBm with a power added efficiency (PAE) of 28% at 2.45 GHz. The measured PAE is higher than 21% at 7-dB power back-off (PBO) levels. Furthermore, under the excitation of 256-quadrature amplitude modulation (QAM) signal, the proposed ADPA achieves a PAE of 22% at an average output power (<inline-formula> <tex-math>$P_{\\text {avg}}$ </tex-math></inline-formula>) of 25.8 dBm with DPD while ensuring that the EVM is better than −32 dB.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 4","pages":"488-491"},"PeriodicalIF":0.0000,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Fully Integrated GaAs MMIC Asymmetric Doherty Power Amplifier With Enhanced Gain Flatness\",\"authors\":\"Xinran Yang;Yi Zhao;Lang Chen;Zeyu Ge;Jiani Zhou;Feng Sun\",\"doi\":\"10.1109/LMWT.2025.3535739\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel fully integrated asymmetric Doherty power amplifier (DPA) with optimized driver is proposed. By adjusting the unequal power divider (UPD) and the bias conditions of two-stage carrier and peak power amplifiers (PPAs), good back-off efficiency (BOE) and gain flatness have been achieved. To validate the proposed concept, a 2.45-GHz asymmetric DPA (ADPA) is fabricated in 2-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) process. Under continuous-wave (CW) measurement, the power amplifier (PA) can provide a saturated output power (<inline-formula> <tex-math>$P_{\\\\text {SAT}}$ </tex-math></inline-formula>) of 32.3 dBm with a power added efficiency (PAE) of 28% at 2.45 GHz. The measured PAE is higher than 21% at 7-dB power back-off (PBO) levels. Furthermore, under the excitation of 256-quadrature amplitude modulation (QAM) signal, the proposed ADPA achieves a PAE of 22% at an average output power (<inline-formula> <tex-math>$P_{\\\\text {avg}}$ </tex-math></inline-formula>) of 25.8 dBm with DPD while ensuring that the EVM is better than −32 dB.\",\"PeriodicalId\":73297,\"journal\":{\"name\":\"IEEE microwave and wireless technology letters\",\"volume\":\"35 4\",\"pages\":\"488-491\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2025-02-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE microwave and wireless technology letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10873287/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"0\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10873287/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A Fully Integrated GaAs MMIC Asymmetric Doherty Power Amplifier With Enhanced Gain Flatness
A novel fully integrated asymmetric Doherty power amplifier (DPA) with optimized driver is proposed. By adjusting the unequal power divider (UPD) and the bias conditions of two-stage carrier and peak power amplifiers (PPAs), good back-off efficiency (BOE) and gain flatness have been achieved. To validate the proposed concept, a 2.45-GHz asymmetric DPA (ADPA) is fabricated in 2-$\mu $ m gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) process. Under continuous-wave (CW) measurement, the power amplifier (PA) can provide a saturated output power ($P_{\text {SAT}}$ ) of 32.3 dBm with a power added efficiency (PAE) of 28% at 2.45 GHz. The measured PAE is higher than 21% at 7-dB power back-off (PBO) levels. Furthermore, under the excitation of 256-quadrature amplitude modulation (QAM) signal, the proposed ADPA achieves a PAE of 22% at an average output power ($P_{\text {avg}}$ ) of 25.8 dBm with DPD while ensuring that the EVM is better than −32 dB.
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