Stress accommodation in nanoscale dolan bridges designed for superconducting qubits

Josephson junctions are the principal circuit element in numerous superconducting quantum information devices and can be readily integrated into large-scale electronics. However, device integration at the wafer scale necessarily depends on having a reliable, high-fidelity, and high-yield fabrication method for creating Josephson junctions. When creating Al/AlO${}_x$ based superconducting qubits, the standard Josephson junction fabrication method relies on a sub-micron suspended resist bridge, known as a Dolan bridge, which tends to be particularly fragile and can often times fracture during the resist development process, ultimately resulting in device failure. In this work, we demonstrate a unique Josephson junction lithography mask design that incorporates stress-relief channels. Our simulation results show that the addition of stress-relief channels reduces the lateral stress in the Dolan bridge by more than 70% for all the bridge geometries investigated. In practice, our novel mask design significantly increased the survivability of the bridge during device processing, resulting in 100% yield for over 100 Josephson junctions fabricated.