Algorithm of the inter-channel mismatches calibration in TIADC

To address the issues in existing algorithms related to calibration accuracy, hardware utilization, or the trade-off between calibration speed and accuracy, this paper proposes a fully digital background calibration method including parallel and serial architecture, which can reduce hardware utilization and supports the expansion to an arbitrary number of channels.

We performed board-level verification on an FPGA for the proposed algorithm. The results of the FPGA board-level verification match those of the MATLAB behavioral simulation. At an input frequency of 0.025 $f_s$, the SNDR and SFDR improved by 8.59 dB and 11.54 dB, respectively, and the effective number of bits (ENOB) increased by 1.42 bits. At an input frequency of 0.05 $f_s$, the SNDR and SFDR improved by 20.89 dB and 13.65 dB, respectively, and the ENOB increased by 2.27 bits. At an input frequency of 0.2 $f_s$, the SNDR and SFDR improved by 11.86 dB and 17.89 dB, respectively, and the ENOB increased by 1.97 bits. The output layout size was 500 μm × 550 μm.