Control of Cu morphology on TaN barrier and combined Ru-TaN barrier/liner substrates for nanoscale interconnects from atomistic kinetic Monte Carlo simulations

The miniaturization of electronic devices poses severe challenges for metal interconnect deposition in back end of line processing due to the decreasing volume available in the interconnect via. Cu is currently used as the interconnect metal and requires barrier and liner layers to prevent diffusion into silicon and promote smooth film growth. However, these layers occupy critical space in the already narrow, high-aspect ratio interconnect vias. Designing combined barrier/liner materials is critical tooptimizingavailable interconnect volume. While film morphology can be predicted from first principles calculations, e.g. Density Functional Theory (DFT), modelling deposition to understand the evolution of metal growth and optimize barrier material design and metal deposition is extremely challenging. We present an atomistic kinetic Monte Carlo (kMC) investigation of Cu deposition on Ru-modified TaN as a potential dual-function barrier/line material. Using DFT-calculated activation barriers, we predict Cu morphology on these technologically important substrates at back end of line processing temperatures. We evaluate 2D vs. 3D morphology and film quality by analyzing film roughness, island size, substrate exposure, layer occupation rate, film compactness and the effect of annealing. Our results show Ru-modified TaN with 50% Ru incorporation significantly reduces roughness and islanding, promoting desired 2D growth. Vacuum annealing further promotes smooth Cu films, eliminating vacancy defects on Ru-modified substrates, while TaN promotes further island formation. This demonstrates the potential of Ru-TaN in optimizing Cu deposition for advanced CMOS interconnects and showcases a new, robust approach for atomistic simulation of metal deposition on a range of substrates.