一种新型的低硬件成本扫描链结构,可抵御扫描卫星攻击

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Fatih Tiryakioğlu , Ahmet Unutulmaz , İhsan Çiçek , Ali Tangel
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引用次数: 0

摘要

逻辑锁用于保护硬件设计不受不可信的制造设备的影响。制造商可以通过使用扫描链结构来执行SAT攻击来绕过保护,该结构旨在增加ic的可测试性。防止这种攻击的一种方法是使用加密算法对扫描链进行加密。但是,在集成电路中添加专用加密模块会增加成本。在本研究中,我们通过重用扫描链结构来实现一种加密算法,即Trivium算法,从而降低了该成本。我们的实现允许由不可靠的测试人员执行生产、功能和任务模式现场测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A novel low-hardware-cost scan chain architecture resilient to scanSAT attack
Logic locking serves to protect a hardware design from an untrusted fabrication facility. A manufacturer may bypass the protection by performing a SAT attack by making use of the scan chain structure, which was designed to increase the testability of ICs. One way to prevent such attacks is to encrypt the scan chain using a cryptographic algorithm. However, adding dedicated encryption modules into the IC increases the cost. In this study, we reduced this cost by reusing the scan chain structure to be able to implement a cryptographic algorithm, the Trivium algorithm. Our implementation allows production, functional and mission mode field tests to be performed by an unreliable tester.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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