Energy efficient high speed dynamic comparators using shared charge logic and auxiliary inverter technique

This work presents two energy efficient, low power dynamic comparators showing an advantage of high speed over the conventional comparator. Both dynamic comparators employ self-cascode technique in the preamplifier stage for improved gain. In the latch stage, the proposed comparator 1 uses shared charge logic technique for low voltage applications while the proposed comparator 2 also combines auxiliary inverters in the later stage in order to improve its speed. The verification of the proposal is done in Cadence Virtuoso simulations at 90 nm CMOS technology node. The proposed comparator 1(2) shows 25.2 (12.6) ps of delay, 24 (39) µW of power and 27.2 (47.4) fJ/conversion of energy. The proposed designs show significant improvements of 80 %, 67 % and 62 % in delay, power and energy respectively. The mismatch analysis for delay, power, energy, offset voltage and kickback noise are also validated using post-layout Monte Carlo analysis is also performed which shows resilience of the proposals.