{"title":"带有自适应偏置的140 ghz CMOS四路功率组合多尔蒂功率放大器","authors":"Junyuan Tu;Guohao He;Aguan Hong;Yuxin Yang;Xiang Yi;Pei Qin;Haoshen Zhu;Wenquan Che;Quan Xue","doi":"10.1109/TCSII.2025.3541202","DOIUrl":null,"url":null,"abstract":"This brief presents a D-band power amplifier (PA) with high output power and high back-off efficiency in 40nm GP CMOS technology. The PA is based on a four-way parallel power-combining Doherty architecture. Two sub-amplifiers with high output power have been realized using a highly balanced impedance-transforming power combiner based on the SLOT-GCPW structure. A transmission-line-like impedance inverter and a quadrature coupler with a slow wave coplanar waveguides (S-CPWs) are proposed to obtain compact size. Meanwhile, the adaptive bias technique is used to overcome the difficulties of implementing conventional Doherty architectures at terahertz (THz). The measured Doherty PA realizes a peak small-signal gain of 15.3 dB with 17 GHz 3-dB bandwidth. At 140 GHz, the PA achieves 16.1 dBm saturated output power (Psat) with peak power-added-efficiency (PAE) of 7% and 3% PAE at 6-dB power back-off (PBO) from Psat. To the authors’ best knowledge, this is the first D-band CMOS integrated PA with high PBO efficiency.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"539-543"},"PeriodicalIF":4.9000,"publicationDate":"2025-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 140-GHz CMOS Four-Way Power Combining Doherty Power Amplifier With Adaptive Biasing\",\"authors\":\"Junyuan Tu;Guohao He;Aguan Hong;Yuxin Yang;Xiang Yi;Pei Qin;Haoshen Zhu;Wenquan Che;Quan Xue\",\"doi\":\"10.1109/TCSII.2025.3541202\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This brief presents a D-band power amplifier (PA) with high output power and high back-off efficiency in 40nm GP CMOS technology. The PA is based on a four-way parallel power-combining Doherty architecture. Two sub-amplifiers with high output power have been realized using a highly balanced impedance-transforming power combiner based on the SLOT-GCPW structure. A transmission-line-like impedance inverter and a quadrature coupler with a slow wave coplanar waveguides (S-CPWs) are proposed to obtain compact size. Meanwhile, the adaptive bias technique is used to overcome the difficulties of implementing conventional Doherty architectures at terahertz (THz). The measured Doherty PA realizes a peak small-signal gain of 15.3 dB with 17 GHz 3-dB bandwidth. At 140 GHz, the PA achieves 16.1 dBm saturated output power (Psat) with peak power-added-efficiency (PAE) of 7% and 3% PAE at 6-dB power back-off (PBO) from Psat. To the authors’ best knowledge, this is the first D-band CMOS integrated PA with high PBO efficiency.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"72 4\",\"pages\":\"539-543\"},\"PeriodicalIF\":4.9000,\"publicationDate\":\"2025-02-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10883342/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10883342/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 140-GHz CMOS Four-Way Power Combining Doherty Power Amplifier With Adaptive Biasing
This brief presents a D-band power amplifier (PA) with high output power and high back-off efficiency in 40nm GP CMOS technology. The PA is based on a four-way parallel power-combining Doherty architecture. Two sub-amplifiers with high output power have been realized using a highly balanced impedance-transforming power combiner based on the SLOT-GCPW structure. A transmission-line-like impedance inverter and a quadrature coupler with a slow wave coplanar waveguides (S-CPWs) are proposed to obtain compact size. Meanwhile, the adaptive bias technique is used to overcome the difficulties of implementing conventional Doherty architectures at terahertz (THz). The measured Doherty PA realizes a peak small-signal gain of 15.3 dB with 17 GHz 3-dB bandwidth. At 140 GHz, the PA achieves 16.1 dBm saturated output power (Psat) with peak power-added-efficiency (PAE) of 7% and 3% PAE at 6-dB power back-off (PBO) from Psat. To the authors’ best knowledge, this is the first D-band CMOS integrated PA with high PBO efficiency.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.