Low Power CMOS Stochastic Bit Based Ising Machine and Its Application to Graph Coloring Problem

The Ising spin model is an efficient method for solving combinatorial optimization problems (COPs) but faces challenges in conventional Von-Neumann architectures due to high computational costs, especially with the growing data volume in the IoT era. To address this problem, we proposed low power CMOS stochastic bit based Ising machine to efficiently compute COPs. By adopting compute-in-memory (CIM) approach for parallel spin computation, we achieved energy efficient spin computing. Furthermore, we harnessed the inherent randomness of CMOS stochastic bit to prevent Ising computing process from being stuck into local minima, effectively mitigating the power penalty associated with the random number generators (RNGs) in the conventional CMOS based Ising machines. We demonstrated the feasibility of our design by solving NP-complete graph coloring problem with four vertices and three colors using TSMC 65 nm GP process. Moreover, the proposed CMOS stochastic bit based spin unit consumes the lowest power/spin among the state-of-the-art Ising machine researches, with power/spin of 1.07 $\mu W$ and energy/spin of 107 fJ.