采用参考采样技术和回路可重构技术的257-nA静态电流200-mA负载低压差稳压器

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Shangzheng Yang, Kefan Qin, Xiang Yan, Haitao Cui, Jianwei Zhao, Wei Ma, Weibo Hu, Member, IEEE
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引用次数: 0

摘要

提出了一种适用于物联网和便携式设备的超低静态电流低差稳压器(LDO)。为了降低基准功耗,将传统的连续导通基准改为间歇导通基准,并利用开关电容存储基准电压,称为基准采样技术(RST)。同时,为了减小LDO主回路的静态电流,采用了环路可重构技术(LRT)。当LDO无负载时,主回路为两级结构,采用小功率晶体管,静态电流低。当负载增加时,主回路变为三级结构,采用大功率晶体管。原型芯片采用0.35 μm CMOS工艺,占地0.6 mm2,静态电流为257 nA。此外,由于瞬态增强电路,当负载电流在1 μS内从0 mA跃迁到200 mA时,输出稳定时间约为10 μS,欠冲电压为160 mV。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 257-nA quiescent current 200-mA load low-dropout regulator with reference sampling technique and loop reconfigurable technique
This paper proposes an ultra-low quiescent current low-dropout regulator (LDO) for Internet-of-Things and portable devices. To reduce power consumption in the reference, the conventional continuous-on reference is replaced by intermittent-on reference, and using switching capacitors to store reference voltage, which called reference sampling technique (RST). Meanwhile, to decrease the quiescent current in LDO main loop, the loop reconfigurable technique (LRT) is implemented. When the LDO with no load, the main loop is two-stage structure with small power transistor, which results in low quiescent current. When a heavy load is added, the main loop is changed into a three-stage structure with large power transistor. A prototype chip is fabricated in 0.35 μm CMOS process, occupying 0.6 mm2 area and consumes 257 nA quiescent current. Furthermore, owing to the transient enhance circuit, when the load current jumps from 0 mA to 200 mA within 1 μS, the output settling time is about 10 μS, with an undershoot voltage of 160 mV.
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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