A digital background calibration method for SAR ADC based on dual-layer feedforward neural network

This paper addresses the impact of capacitor mismatch, comparator offset, and incomplete settling of the digital-to-analog converter (DAC) on the dynamic performance of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). A digital background calibration method using a double-layer feedforward neural network is proposed. The network is trained in MATLAB and implemented on an FPGA to validate the calibration algorithm. The study explores the influence of parameters like the number of neurons, training samples, and iterations on performance. FPGA results show that, after calibration, the Spurious-Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of a 12-bit 100 MSPS SAR ADC model improved from 46.58 dB and 46.53 dB to 98.10 dB and 70.87 dB. Similarly, for a 10-bit 31.25 MSPS SAR ADC chip, SFDR and SNDR increased from 61.46 dB and 46.86 dB to 79.87 dB and 57.09 dB. These results confirm the proposed method’s effectiveness for addressing non-idealities in both simulated models and hardware.