ASIC Design of a Canonical Huffman Encoder for Computational Storage Drives

Huffman coding is foundational to data compression algorithms. We propose an advanced application-specific integrated circuit (ASIC) design for a canonical Huffman encoder, optimised for high throughput and low power consumption. Our design introduces a high-speed sorting circuit, an efficient Huffman tree canonisation algorithm and an innovative entropy-based compressibility prediction mechanism. Implemented using 12 nm CMOS technology, the proposed solution achieves a remarkable throughput of 4 GB/s and sub-microsecond latency for 4 KB pages, outperforming existing x86 software implementations by nearly two orders of magnitude and surpassing state-of-the-art hardware accelerators. This advancement significantly enhances data processing capabilities in computational storage drives (CSDs), providing a scalable and energy-efficient data compression solution for modern data centres.