一种用于CMOS图像传感器的剩余脉冲展宽插值量化列级ADC架构

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-03-15 DOI:10.1016/j.mejo.2025.106638

Qiang Zhao , Ziming Wang , Chunhui Fan , Bin Qiang , Jitao Xu , Xin Li , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu

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引用次数: 0

摘要

为了进一步提高图像传感器读出电路的速度，减少对图像传感器读出电路的面积占用，本文提出了一种基于脉冲展宽技术的两步ADC架构。在本设计中，采用RC结构时间放大器（TA）对SSADC的剩余脉冲进行展宽，然后进行量化。SSADC的211个量化周期可以缩短为27+24个量化周期（7位粗量化，4位细量化），量化时间减少93%。同时，由于部分电路列共用，电路功耗仅为75.05 uW。在130 nm CMOS工艺下对电路进行了仿真。模拟电源和数字电源分别为3v和1.2 V。主时钟频率200MHz，最小时间分辨率312.5ps。电路的DNL和INL分别为-0.2/+ 0.4 LSB和0/+1 LSB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A residual pulse broadening interpolation quantization column-level ADC architecture for CMOS image sensors

To further improve the speed of the image sensor readout circuit and reduce the area occupation, this paper proposes a two-step ADC architecture based on pulse broadening technology. In this design, the residual pulse of SSADC is broadened by RC structure Time amplifier(TA), and then quantified. The 2¹¹ quantization cycles of SSADC can be shortened to 2⁷+2⁴ quantization cycles ( 7-bit coarse quantization, 4-bit fine quantization ), reducing the quantization time by 93 %. At the same time, due to the sharing of some circuit columns, the power consumption of the circuit is only 75.05 uW. The circuit is simulated in 130 nm CMOS process. The analog power supply and digital power supply are 3 V and 1.2 V. The main clock frequency is 200MHz, and the minimum time resolution is 312.5ps. The DNL and INL of the circuit are -0.2/+ 0.4 LSB and 0/+1 LSB.

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.