A low power SAR ADC with fine–tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS

This work proposes an adaptive sampling SAR Analog-to-Digital converter (ADC) with a novel fine-tuned time-based sampling technique to dynamically adjust the sample rate for normal and abnormal ECG signals based on the characteristics of the incoming ECG signal. By integrating machine learning, the ADC adapts to varying signal conditions, ensuring accurate capture of essential data while maintaining energy efficiency, thereby enhancing the effectiveness of portable and wearable health monitoring devices. Unlike conventional methods, the Analog front end uses a time-based technique that effectively identifies and digitizes all critical information present in ECG signals. Additionally, the ADC incorporates a variable resolution scheme, enhancing power efficiency and reducing data bandwidth. The ADC adaptively allocates more bits to the most significant portions of the ECG waveform while reducing the resolution for less critical segments by employing a time-based approach. This enables efficient data representation and reduces overall data transfer requirements, making this architecture more power-efficient. Implemented in 180 nm CMOS technology, the proposed ADC consumes only 498.6 μW with a 1.8 V supply and achieves ENOB of 5.21 bits, SNDR of 31.76 dB, and SFDR of 44.31 dB. The sampling frequency of the proposed architecture changes from 64 Hz to 512 Hz, which is suitable for portable ECG monitoring applications. The FoM of the proposed work ranges from 100 to 262 fj/conversion-step for 64–512 Hz sampling rate, respectively.