使用Intel QAT的硬件加速内核空间内存压缩

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Qirong Xia;Houxiang Ji;Yang Zhou;Nam Sung Kim
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引用次数: 0

摘要

数据压缩技术被广泛应用于数据中心,不仅可以减少内存和存储容量的消耗,还可以减少互连带宽的消耗。尽管如此,用于数据压缩的CPU周期明显增加了数据中心的总体负担。为了为数据中心提供经济高效的数据压缩能力,英特尔推出了QuickAssist Technology (QAT),这是一种附着在pcie上的数据压缩加速器。在这项工作中,我们首先全面评估了最新的片上QAT加速器的压缩/解压缩性能,然后将其与上一代片外QAT加速器进行了比较。随后,作为QAT的一个引人注目的应用程序,我们采用Linux内存优化内核特性:交换页面压缩缓存(zswap),重新实现它以有效地使用QAT,然后比较基于QAT的zswap与基于cpu的zswap的性能。我们的评估表明,部署基于cpu的zswap会使共同运行的对延迟敏感的应用程序Redis的尾部延迟增加3.2-12.1倍,而基于qat的zswap与不部署zswap相比,并没有明显增加尾部延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hardware-Accelerated Kernel-Space Memory Compression Using Intel QAT
Data compression has been widely used by datacenters to decrease the consumption of not only the memory and storage capacity but also the interconnect bandwidth. Nonetheless, the CPU cycles consumed for data compression notably contribute to the overall datacenter taxes. To provide a cost-efficient data compression capability for datacenters, Intel has introduced QuickAssist Technology (QAT), a PCIe-attached data-compression accelerator. In this work, we first comprehensively evaluate the compression/decompression performance of the latest on-chip QAT accelerator and then compare it with that of the previous-generation off-chip QAT accelerator. Subsequently, as a compelling application for QAT, we take a Linux memory optimization kernel feature: compressed cache for swap pages (zswap), re-implement it to use QAT efficiently, and then compare the performance of QAT-based zswap with that of CPU-based zswap. Our evaluation shows that the deployment of CPU-based zswap increases the tail latency of a co-running latency-sensitive application, Redis by 3.2-12.1×, while that of QAT-based zswap does not notably increase the tail latency compared to no deployment of zswap.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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