具有SiGe BiCMOS谐波抑制增强的d波段×8倍频器

0 ENGINEERING, ELECTRICAL & ELECTRONIC
Xianhu Luo;Xu Cheng;Jiangan Han;Weikang Zhou;Yunbo Rao;Liang Zhang;Fengjun Chen;Binbin Cheng;Xianjin Deng
{"title":"具有SiGe BiCMOS谐波抑制增强的d波段×8倍频器","authors":"Xianhu Luo;Xu Cheng;Jiangan Han;Weikang Zhou;Yunbo Rao;Liang Zhang;Fengjun Chen;Binbin Cheng;Xianjin Deng","doi":"10.1109/LMWT.2024.3515486","DOIUrl":null,"url":null,"abstract":"In this letter, a D-band frequency octupler (<inline-formula> <tex-math>$\\times 8$ </tex-math></inline-formula>) with high harmonic suppression is presented in a 0.13-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m SiGe BiCMOS technology. To enhance the suppression of even harmonics among high harmonics, we have implemented and refined a waveform shaping technique that effectively elevates the second harmonic while suppressing the fourth, sixth, and higher even harmonics. Additionally, the transformer-based bandpass filters (BPFs) are integrated into the design of the <inline-formula> <tex-math>$\\times 8$ </tex-math></inline-formula> frequency multiplier to enhance the suppression of nontarget frequency signals without compromising power consumption. To validate our proposed concept, a D-band <inline-formula> <tex-math>$\\times 8$ </tex-math></inline-formula> frequency multiplier operating at 114.5–140 GHz is manufactured in a SiGe process. The circuit achieved an output power of −2.5 dBm with an input power of −2 dBm. Within the 3-dB bandwidth, the suppression of various harmonics exceeded 28 dBc and with the maximum suppression exceeding 38 dBc. The chip consumed 125 mW of power and occupied an area of <inline-formula> <tex-math>$0.63\\times 1.2$ </tex-math></inline-formula> mm2.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"35 3","pages":"314-317"},"PeriodicalIF":0.0000,"publicationDate":"2025-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A D-Band ×8 Frequency Multiplier With Harmonic Suppression Enhancements in SiGe BiCMOS\",\"authors\":\"Xianhu Luo;Xu Cheng;Jiangan Han;Weikang Zhou;Yunbo Rao;Liang Zhang;Fengjun Chen;Binbin Cheng;Xianjin Deng\",\"doi\":\"10.1109/LMWT.2024.3515486\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this letter, a D-band frequency octupler (<inline-formula> <tex-math>$\\\\times 8$ </tex-math></inline-formula>) with high harmonic suppression is presented in a 0.13-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m SiGe BiCMOS technology. To enhance the suppression of even harmonics among high harmonics, we have implemented and refined a waveform shaping technique that effectively elevates the second harmonic while suppressing the fourth, sixth, and higher even harmonics. Additionally, the transformer-based bandpass filters (BPFs) are integrated into the design of the <inline-formula> <tex-math>$\\\\times 8$ </tex-math></inline-formula> frequency multiplier to enhance the suppression of nontarget frequency signals without compromising power consumption. To validate our proposed concept, a D-band <inline-formula> <tex-math>$\\\\times 8$ </tex-math></inline-formula> frequency multiplier operating at 114.5–140 GHz is manufactured in a SiGe process. The circuit achieved an output power of −2.5 dBm with an input power of −2 dBm. Within the 3-dB bandwidth, the suppression of various harmonics exceeded 28 dBc and with the maximum suppression exceeding 38 dBc. The chip consumed 125 mW of power and occupied an area of <inline-formula> <tex-math>$0.63\\\\times 1.2$ </tex-math></inline-formula> mm2.\",\"PeriodicalId\":73297,\"journal\":{\"name\":\"IEEE microwave and wireless technology letters\",\"volume\":\"35 3\",\"pages\":\"314-317\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2025-01-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE microwave and wireless technology letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10829964/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"0\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10829964/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本文介绍了一种采用0.13- $\mu $ m SiGe BiCMOS技术的高谐波抑制的d波段频率八倍器($\ × 8$)。为了增强对高次谐波中的均匀谐波的抑制,我们实现并改进了一种波形整形技术,该技术可以有效地提高二次谐波,同时抑制四次、六次和更高的均匀谐波。此外,基于变压器的带通滤波器(bpf)集成到$\times 8$倍频器的设计中,以增强对非目标频率信号的抑制,同时不影响功耗。为了验证我们提出的概念,在SiGe工艺中制造了工作在114.5-140 GHz的d波段$\乘以8$倍频器。电路输出功率为−2.5 dBm,输入功率为−2dbm。在3db带宽内,对各种谐波的抑制超过28dbc,最大抑制超过38dbc。该芯片消耗125兆瓦的功率,占地面积为0.63 × 1.2 mm2美元。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A D-Band ×8 Frequency Multiplier With Harmonic Suppression Enhancements in SiGe BiCMOS
In this letter, a D-band frequency octupler ( $\times 8$ ) with high harmonic suppression is presented in a 0.13- $\mu $ m SiGe BiCMOS technology. To enhance the suppression of even harmonics among high harmonics, we have implemented and refined a waveform shaping technique that effectively elevates the second harmonic while suppressing the fourth, sixth, and higher even harmonics. Additionally, the transformer-based bandpass filters (BPFs) are integrated into the design of the $\times 8$ frequency multiplier to enhance the suppression of nontarget frequency signals without compromising power consumption. To validate our proposed concept, a D-band $\times 8$ frequency multiplier operating at 114.5–140 GHz is manufactured in a SiGe process. The circuit achieved an output power of −2.5 dBm with an input power of −2 dBm. Within the 3-dB bandwidth, the suppression of various harmonics exceeded 28 dBc and with the maximum suppression exceeding 38 dBc. The chip consumed 125 mW of power and occupied an area of $0.63\times 1.2$ mm2.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
CiteScore
6.00
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信