A CMOS Linear Low-Noise Amplifier Using Transformer-Based Second-Harmonic Trap

This letter presents second-harmonic termination techniques for inductively source-degenerated cascode CMOS low-noise amplifiers (LNAs) with a transformer (TF)-based harmonic network. The proposed harmonic trap circuit terminates the second-order distortion generated in the common-source stage of the cascode structure, thereby improving the linearity of the LNA. In a transformed-based harmonic trap circuit, the primary inductor of the TF is used as the source-degenerated inductor for fundamental frequency gain and noise matching, and the secondary inductor along with an additional capacitor is used to terminate the second-harmonic frequency through LC resonance. The LNA is implemented using a 90-nm CMOS process and includes on-chip electrostatic discharge (ESD) protection circuits, making it suitable for commercialization. The fabricated LNA achieves a small signal gain of 18.48 dB, a noise figure (NF) of 1.1 dB, and an third input intercept point (IIP3) performance of -5.9 dBm at 2.62 GHz. The chip has an area of $416\times 879~\mu $ m2 excluding the guard-ring layer, and it consumes 11.76 mW of power at a supply voltage of 1.2 V.