Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems

A secure random number generator (RNG) is crucial for cryptography and data protection applications. Many existing approaches employ classical chaotic systems, which have been demonstrated as vulnerable to some attacks. Therefore, this research proposes the design on FPGA of a new pseudo-RNG based on an artificial neural network (ANN) and chaotic systems. Initially, a multi-layer perceptron (MLP) with a hardware friendly activation function (AF) is trained to mimic the behavior of the unified chaotic system (UCS). To mitigate chaos degradation and the difference between the training and the inference, the scheduled sampling technique is adapted and applied to the MLP network. Once the model is well-tuned, its chaotic nature is validated by calculating the Lyapunov exponents and determining the fractal dimension. The pre-trained model based on which an MLP-based Chaotic Pseudo-RNG (MLP-CPRNG) is then implemented on FPGA using VHDL language and Xilinx Vivado design suite. To improve the generator’s output capabilities, a technique named the $d$-lagged differencing ($d$-LD) is implemented as a part of the MLP-CPRNG. The implemented MLP-CPRNG outperforms the existing works in terms of resource utilization, which makes it suitable for resource-constrained environment. It also offers extended key space and has successfully passed performance tests such as NIST statistical tests, entropy measurement, and correlation analysis. These results highlight the robustness of MLP-CPRNG against brute-force, algebraic and statistical attacks, thus its suitability for embedded cryptographic applications.