{"title":"锗基双金属栅异质介质TFET的离子/离合及跨导优化","authors":"D. Gracia , D. Jackuline Moni , D. Nirmal","doi":"10.1016/j.micrna.2025.208128","DOIUrl":null,"url":null,"abstract":"<div><div>This simulation study delves in to the exploration of Tunnel Field Effect Transistors (TFET) with Dual Metal Gate (DMG) hetero-dielectric structure incorporating a Germanium channel using simulations study in TCAD. The device efficiency measures such as current in the off-state (I<sub>off</sub>), on-state current (I<sub>on</sub>), switching efficiency of the current (I<sub>on</sub>/I<sub>off</sub>) are observed for the proposed device. The metrics are taken in comparison with the traditional DMG hetero-dielectric MOSFET. The recommended device exhibits a 74.8 % reduction in the Subthreshold Slope (SS) compared to the traditional DMG hetero-dielectric MOSFET. An enhanced I<sub>on</sub>/I<sub>off</sub> ratio of 4.669 × 10<sup>8</sup>for Ge channel TFET is observed over a conventional DMG MOSFET simulated under same environmental conditions. The performance analysis has been carried out for various channel thickness (t<sub>ch</sub>), oxide thickness (t<sub>ox</sub>), tunneling lengths (L1:L2) and different gate metal work functions. A detailed RF analysis for hetero dielectrics with HfO<sub>2</sub> near the source area and SiO<sub>2</sub> near the drain area is carried out for DMG Hetero Dielectric TFET. It is evident that positioning the low-k dielectric in close proximity to the drain region leads to the suppression of parasitic capacitances such as C<sub>gd</sub> and C<sub>gg</sub>. This characteristic enhances its suitability as a superior aspirant for nano digital applications.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"202 ","pages":"Article 208128"},"PeriodicalIF":2.7000,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Optimisation of Ion/Ioff and transconductance of germanium based dual metal gate hetero-dielectric TFET\",\"authors\":\"D. Gracia , D. Jackuline Moni , D. Nirmal\",\"doi\":\"10.1016/j.micrna.2025.208128\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This simulation study delves in to the exploration of Tunnel Field Effect Transistors (TFET) with Dual Metal Gate (DMG) hetero-dielectric structure incorporating a Germanium channel using simulations study in TCAD. The device efficiency measures such as current in the off-state (I<sub>off</sub>), on-state current (I<sub>on</sub>), switching efficiency of the current (I<sub>on</sub>/I<sub>off</sub>) are observed for the proposed device. The metrics are taken in comparison with the traditional DMG hetero-dielectric MOSFET. The recommended device exhibits a 74.8 % reduction in the Subthreshold Slope (SS) compared to the traditional DMG hetero-dielectric MOSFET. An enhanced I<sub>on</sub>/I<sub>off</sub> ratio of 4.669 × 10<sup>8</sup>for Ge channel TFET is observed over a conventional DMG MOSFET simulated under same environmental conditions. The performance analysis has been carried out for various channel thickness (t<sub>ch</sub>), oxide thickness (t<sub>ox</sub>), tunneling lengths (L1:L2) and different gate metal work functions. A detailed RF analysis for hetero dielectrics with HfO<sub>2</sub> near the source area and SiO<sub>2</sub> near the drain area is carried out for DMG Hetero Dielectric TFET. It is evident that positioning the low-k dielectric in close proximity to the drain region leads to the suppression of parasitic capacitances such as C<sub>gd</sub> and C<sub>gg</sub>. This characteristic enhances its suitability as a superior aspirant for nano digital applications.</div></div>\",\"PeriodicalId\":100923,\"journal\":{\"name\":\"Micro and Nanostructures\",\"volume\":\"202 \",\"pages\":\"Article 208128\"},\"PeriodicalIF\":2.7000,\"publicationDate\":\"2025-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Micro and Nanostructures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S2773012325000573\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"PHYSICS, CONDENSED MATTER\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012325000573","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}
Optimisation of Ion/Ioff and transconductance of germanium based dual metal gate hetero-dielectric TFET
This simulation study delves in to the exploration of Tunnel Field Effect Transistors (TFET) with Dual Metal Gate (DMG) hetero-dielectric structure incorporating a Germanium channel using simulations study in TCAD. The device efficiency measures such as current in the off-state (Ioff), on-state current (Ion), switching efficiency of the current (Ion/Ioff) are observed for the proposed device. The metrics are taken in comparison with the traditional DMG hetero-dielectric MOSFET. The recommended device exhibits a 74.8 % reduction in the Subthreshold Slope (SS) compared to the traditional DMG hetero-dielectric MOSFET. An enhanced Ion/Ioff ratio of 4.669 × 108for Ge channel TFET is observed over a conventional DMG MOSFET simulated under same environmental conditions. The performance analysis has been carried out for various channel thickness (tch), oxide thickness (tox), tunneling lengths (L1:L2) and different gate metal work functions. A detailed RF analysis for hetero dielectrics with HfO2 near the source area and SiO2 near the drain area is carried out for DMG Hetero Dielectric TFET. It is evident that positioning the low-k dielectric in close proximity to the drain region leads to the suppression of parasitic capacitances such as Cgd and Cgg. This characteristic enhances its suitability as a superior aspirant for nano digital applications.