Jamie C. Ye;Alain H. Antón;Sanaz Sadeghi;Russ H. Huang;Alyosha C. Molnar
{"title":"同时双载波变压器耦合无源混频器优先接收器前端支持阻塞抑制","authors":"Jamie C. Ye;Alain H. Antón;Sanaz Sadeghi;Russ H. Huang;Alyosha C. Molnar","doi":"10.1109/JSSC.2025.3546082","DOIUrl":null,"url":null,"abstract":"A high dynamic range N-path passive mixer-first receiver architecture capable of simultaneously down-converting two arbitrary bands through a single RF port is presented. The architecture consists of two passive mixers arranged in a series configuration with a transformer front-end to minimize cross-loading between mixers while still providing impedance transparency and associated interference suppression for both bands. A four-phase demonstration in a 16-nm FinFET process operating from 2.8 to 4.3 GHz achieved 6.8–9.7-dB noise figure (NF), 8.9-dBm out-of-band (OOB) blocker compression (B1dB), and 18.6-dBm OOB input-referred third-order intercept point (IIP3) with 25–28 mW of power consumption per channel. When one of the mixers and the corresponding LO are configured to target a blocker, up to 14.4-dBm OOB-B1dB and 27.6-dBm OOB-IIP3 is achieved. This article elaborates on the analysis and design of the initial prototype and presents a new eight-phase prototype using the same general architecture but with improved performance. The new design operating from 2.6 to 3.9 GHz achieves 4.0–7.6-dB NF, 12.5-dBm OOB-B1dB, and 22.1-dBm OOB-IIP3 with 42–47 mW of power consumption per channel.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 5","pages":"1541-1553"},"PeriodicalIF":5.6000,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression\",\"authors\":\"Jamie C. Ye;Alain H. Antón;Sanaz Sadeghi;Russ H. Huang;Alyosha C. Molnar\",\"doi\":\"10.1109/JSSC.2025.3546082\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high dynamic range N-path passive mixer-first receiver architecture capable of simultaneously down-converting two arbitrary bands through a single RF port is presented. The architecture consists of two passive mixers arranged in a series configuration with a transformer front-end to minimize cross-loading between mixers while still providing impedance transparency and associated interference suppression for both bands. A four-phase demonstration in a 16-nm FinFET process operating from 2.8 to 4.3 GHz achieved 6.8–9.7-dB noise figure (NF), 8.9-dBm out-of-band (OOB) blocker compression (B1dB), and 18.6-dBm OOB input-referred third-order intercept point (IIP3) with 25–28 mW of power consumption per channel. When one of the mixers and the corresponding LO are configured to target a blocker, up to 14.4-dBm OOB-B1dB and 27.6-dBm OOB-IIP3 is achieved. This article elaborates on the analysis and design of the initial prototype and presents a new eight-phase prototype using the same general architecture but with improved performance. The new design operating from 2.6 to 3.9 GHz achieves 4.0–7.6-dB NF, 12.5-dBm OOB-B1dB, and 22.1-dBm OOB-IIP3 with 42–47 mW of power consumption per channel.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"60 5\",\"pages\":\"1541-1553\"},\"PeriodicalIF\":5.6000,\"publicationDate\":\"2025-03-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10915566/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10915566/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A high dynamic range N-path passive mixer-first receiver architecture capable of simultaneously down-converting two arbitrary bands through a single RF port is presented. The architecture consists of two passive mixers arranged in a series configuration with a transformer front-end to minimize cross-loading between mixers while still providing impedance transparency and associated interference suppression for both bands. A four-phase demonstration in a 16-nm FinFET process operating from 2.8 to 4.3 GHz achieved 6.8–9.7-dB noise figure (NF), 8.9-dBm out-of-band (OOB) blocker compression (B1dB), and 18.6-dBm OOB input-referred third-order intercept point (IIP3) with 25–28 mW of power consumption per channel. When one of the mixers and the corresponding LO are configured to target a blocker, up to 14.4-dBm OOB-B1dB and 27.6-dBm OOB-IIP3 is achieved. This article elaborates on the analysis and design of the initial prototype and presents a new eight-phase prototype using the same general architecture but with improved performance. The new design operating from 2.6 to 3.9 GHz achieves 4.0–7.6-dB NF, 12.5-dBm OOB-B1dB, and 22.1-dBm OOB-IIP3 with 42–47 mW of power consumption per channel.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.