一种完全透明、灵活和紧凑的低压TFT模型,用于实现全加减法器

Mukuljeet Singh Mehrolia;Ankit Verma;Abhishek Kumar Singh;Nitesh K. Chourasia;Amritanshu Pandey
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摘要

在本文中,使用Silvaco-Atlas工具模拟了一个低压,全透明,柔性薄膜晶体管(TFT),其中无定形铟镓锌氧化物(a- igzo)和HfO2用作TFT的有源层,栅极介电体,铟锡氧化物(ITO)作为源极,漏极和栅极触点的电极。此外,通过Silvaco-Techmodeler和Silvaco-Gateway工具,该TFT被紧凑地建模并用于全加法器和全减法器电路的实现。该技术的计算机辅助设计(TCAD)模拟器件工作电压为2v,具有良好的性能参数,如低阈值电压为0.104 V,高迁移率(~8.9 cm2/V-sec),高$I_{\text {ON}}$ / $I_{\text {OFF}}~ $I_{\text {OFF}} $ 10^{5}$,低亚阈值斜率(SS)为65 mV/decade。Silvaco-Gateway工具用于执行完整的加法器和减法器电路。对于所有8个输入(从000到111),它在分析和、进位、差和借等相应输出时提供了相当可接受的瞬态特性。Silvaco-Techmodeler工具有助于模拟设备的紧凑建模,并产生高达100%的高精度,模拟和建模数据之间的误差非常小(分别为0.41%和0.94%)。这种模拟的、紧凑建模的TFT将在不久的将来用于分析复杂的模拟和数字电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Proposed Fully Transparent, Flexible, and Compact Modeled Low-Voltage TFT for Implementation of Full Adder and Subtractor
In this article, a low-voltage, fully transparent, flexible thin-film transistor (TFT) is simulated using the Silvaco-Atlas tool, in which amorphous indium-gallium–zinc oxide (a-IGZO) and HfO2 are used as the active layers, gate dielectrics of the TFT, and indium-tin oxide (ITO) serves as the electrodes for source, drain, and gate contacts. In addition, this TFT is compactly modeled and used in the implementation of full adder and full subtractor circuits through the Silvaco-Techmodeler and Silvaco-Gateway tools. The technology computer-aided design (TCAD) simulated device has an operating voltage of 2 V and good performance parameters, such as a low threshold voltage of 0.104 V, high mobility (~8.9 cm2/V-sec), high $I_{\text {ON}}$ / $I_{\text {OFF}}~\sim 10^{5}$ , and a low subthreshold slope (SS) of 65 mV/decade. The Silvaco-Gateway tool is used for the execution of full adder and subtractor circuits. For all eight inputs (from 000 to 111), it gives quite acceptable transient characteristics in analyzing corresponding outputs as sum, carry, difference, and borrow. Silvaco-Techmodeler tools help in the compact modeling of simulated devices and generate a high level of accuracy of ~100% with very minimal error between simulated and modeled data (0.41% and 0.94%, respectively). This simulated, compactly modeled TFT would be used in the near future for analyzing complex analog and digital circuits.
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