A 0.35–0.5-V 0.0136-mm² 12 -MHz Digital Frequency-Locked Loop With 1.06%/V Line Sensitivity in 65-nm CMOS

This brief presents a fully integrated sub-0.5 V digital frequency-locked loop (DFLL) incorporating a clock-boosting RC network to secure frequency accuracy under ultra-low voltage (ULV) operation. It embodies 3 key features: 1) a clock-boosting RC network with a time constant $\tau $ = RC to set the nominal frequency, 2) a dynamic tail-boosted comparator with offset background calibration to facilitate operation in ULV regime, and 3) a hybrid digital-controlled oscillator (DCO) with resolution enhancement to uphold the frequency stability. Fabricated in 65-nm CMOS, the DFLL features a compact footprint of 0.0136 mm2 and consumes $5.7~\mu $ W under 0.35 V at room temperature. It achieves a line sensitivity of 1.06%/V across 0.35 to 0.5 V, and a frequency inaccuracy of 176 ppm/°C between −30 and 120 ° C. Benefitting from the offset calibration technique to reduce the inband noise, the DFLL demonstrates outstanding jitter $Fo{\mathrm { M}}_{\mathrm { Jitter}}$ of −224.5 dB and Allan deviation floor of <5 ppm, showcasing exceptional frequency stability.