采用人工耦合谐振腔的谐波抑制GaN功率放大器

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-11-27 DOI:10.1109/TVLSI.2024.3487002

Letian Guo;Jincheng Zhang;Lihe Nie;Jian Wang;Yong Chen;Junyan Ren;Shunli Ma

{"title":"采用人工耦合谐振腔的谐波抑制GaN功率放大器","authors":"Letian Guo;Jincheng Zhang;Lihe Nie;Jian Wang;Yong Chen;Junyan Ren;Shunli Ma","doi":"10.1109/TVLSI.2024.3487002","DOIUrl":null,"url":null,"abstract":"This brief presents an 11.5–17.5-GHz power amplifier (PA) with 32-dBm output power in a 0.25-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m gallium nitride (GaN) process. Capacitively and inductively coupled resonators are used for impedance matching to achieve a flat in-band power gain and a high out-of-band rejection. Meanwhile, the output matching network provides a second-harmonic suppression to improve the average efficiency within the bandwidth of the PA. The measurements show that the proposed PA exhibits an output power of 31–32.5 dBm and a power gain of more than 10.5 dB from 11.5 to 17.5 GHz. Due to the matching networks providing convenient dc feed and dc block, the chip dimension is only <inline-formula> <tex-math>$2.1\\times 1.1$ </tex-math></inline-formula> mm2, corresponding to a power density of 0.77 W/mm2. The proposed PA demonstrates a competitive fractional bandwidth and power density in GaN PA monolithic microwave integrated circuits (MMICs).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"882-886"},"PeriodicalIF":2.8000,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator\",\"authors\":\"Letian Guo;Jincheng Zhang;Lihe Nie;Jian Wang;Yong Chen;Junyan Ren;Shunli Ma\",\"doi\":\"10.1109/TVLSI.2024.3487002\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This brief presents an 11.5–17.5-GHz power amplifier (PA) with 32-dBm output power in a 0.25-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m gallium nitride (GaN) process. Capacitively and inductively coupled resonators are used for impedance matching to achieve a flat in-band power gain and a high out-of-band rejection. Meanwhile, the output matching network provides a second-harmonic suppression to improve the average efficiency within the bandwidth of the PA. The measurements show that the proposed PA exhibits an output power of 31–32.5 dBm and a power gain of more than 10.5 dB from 11.5 to 17.5 GHz. Due to the matching networks providing convenient dc feed and dc block, the chip dimension is only <inline-formula> <tex-math>$2.1\\\\times 1.1$ </tex-math></inline-formula> mm2, corresponding to a power density of 0.77 W/mm2. The proposed PA demonstrates a competitive fractional bandwidth and power density in GaN PA monolithic microwave integrated circuits (MMICs).\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":\"33 3\",\"pages\":\"882-886\"},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-11-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10767417/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10767417/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了一种采用0.25- $\mu $ m氮化镓（GaN）工艺，输出功率为32 dbm的11.5 - 17.5 ghz功率放大器（PA）。电容和电感耦合谐振器用于阻抗匹配，以实现平坦的带内功率增益和高带外抑制。同时，输出匹配网络提供二次谐波抑制，以提高放大器带宽内的平均效率。测量结果表明，该放大器在11.5 ~ 17.5 GHz范围内的输出功率为31 ~ 32.5 dBm，功率增益大于10.5 dB。由于匹配网络提供方便的直流馈电和直流模块，芯片尺寸仅为2.1 × 1.1美元mm2，对应的功率密度为0.77 W/mm2。所提出的PA在GaN PA单片微波集成电路（mmic）中具有竞争力的分数带宽和功率密度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator

This brief presents an 11.5–17.5-GHz power amplifier (PA) with 32-dBm output power in a 0.25-

$\mu $

m gallium nitride (GaN) process. Capacitively and inductively coupled resonators are used for impedance matching to achieve a flat in-band power gain and a high out-of-band rejection. Meanwhile, the output matching network provides a second-harmonic suppression to improve the average efficiency within the bandwidth of the PA. The measurements show that the proposed PA exhibits an output power of 31–32.5 dBm and a power gain of more than 10.5 dB from 11.5 to 17.5 GHz. Due to the matching networks providing convenient dc feed and dc block, the chip dimension is only

$2.1\times 1.1$

mm2, corresponding to a power density of 0.77 W/mm2. The proposed PA demonstrates a competitive fractional bandwidth and power density in GaN PA monolithic microwave integrated circuits (MMICs).

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.