一种单端高压兼容的11位电流转向数模转换器,用于电力数据线网络的自适应噪声消除

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Felix Burkhardt;Florian Protze;Frank Ellinger
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引用次数: 0

摘要

汽车以太网被认为是未来车载数据通信的支柱。它的一个主要特点是能够通过数据线(PoDL)同时传输数据和能量。本文提出了一种单端高电压(HV)兼容的11位电流转向数模转换器(DAC)的设计。该转换器专为在PoDL网络的自适应噪声消除滤波器中用作数字控制电流源而设计。DAC采用符合高压标准的180纳米双极互补金属氧化物半导体(BiCMOS)半导体技术设计,具有两个相同的10位低压(LV)电流导向DAC的单片组合拓扑结构,提供1.8 V电压和两个互补的符合高压标准的输出电流级。分段式低压DAC的主要设计特点是采用单端电流单元,优化开关逻辑,提高单元的瞬态性能和能量效率。此外,研究了一种新导出的$Q^{4}$不对称旋转行走切换方案。在最大输出电压为60 V时,所提出的DAC可以提供双向输出电流,幅度高达500 mA。与相关工作相比,所提出的DAC具有最高的电压顺应性和最高的输出电流。它还具有第二高的分辨率。在采样率为10 MS/s,分辨率为11比特的情况下,100 kHz合成单音的无杂散动态范围(SFDR)可达57.8 dB,最大积分非线性(INL)误差为1.61 LSB,最大微分非线性(DNL)误差为1.05 LSB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Single-Ended High-Voltage-Compliant 11-bit Current-Steering Digital-to-Analog Converter for Adaptive Noise Cancellation in Power Over Data Line Networks
Automotive Ethernet is considered to be the backbone of future in-vehicle data communication. One main feature is its ability to simultaneously transmit data and energy via power over data lines (PoDL). This article proposes the design of a single-ended high-voltage (HV)-compliant 11-bit current-steering digital-to-analog converter (DAC). The converter is tailored for the utilization as digitally controlled current source in an adaptive noise-cancellation filter for PoDL networks. Designed in an HV-compliant 180-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) semiconductor technology, the DAC features a monolithically combined topology of two identical 10-bit low-voltage (LV) current-steering DACs supplied at 1.8 V and two complementary HV-compliant output current stages. Main design features of the segmented LV DAC are the utilization of single-ended current cells with an optimized switching logic, proposed to enhance the cells transient performance and energy efficiency. Furthermore, a newly derived $Q^{4}$ asymmetric rotated walk switching scheme is investigated. At a maximum output voltage of 60 V, the proposed DAC can deliver a bidirectional output current with the amplitudes of up to 500 mA. The proposed DAC exhibits the highest voltage compliance combined with the highest output current compared with related works. It also features the second highest resolution. Operated at a sample rate of 10 MS/s with a resolution of 11 bit, a spurious-free dynamic range (SFDR) of 57.8 dB could be measured for a synthesized single tone at 100 kHz, as well as a maximum integral nonlinearity (INL) error of 1.61 LSB and a differential nonlinearity (DNL) error of 1.05 LSB.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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