SmartDeCoup: Decoupling the STT-RAM LLC for even write distribution and lifetime improvement

Static Random Access Memory (SRAM) based Last Level Caches (LLCs) is losing its edge to Non-Volatile Memories (NVMs) like Spin-Transfer Torque RAM (STT-RAM) which offer advantages including higher density and lower static power consumption. However, they have drawbacks, namely, higher write latency, higher write power consumption, and lower write endurance. Uneven distribution of writes leads to reduced write endurance. Existing endurance enhancement techniques focus on reducing write variation to extend the lifetime. Additionally, these techniques cannot be implemented on top of recent secure cache designs that protect LLCs from timing channel attacks. They cannot prevent recently proposed endurance attacks on the STT-RAM LLC. SmartDeCoup proposes a decoupled tag/data array structure for STT-RAM LLCs and, on top of this structure, introduces two approaches to enhance LLC lifetime through: (a) the Primal Approach, and (b) the Hardware Efficient Approach. The Primal Approach achieves a maximum relative lifetime improvement of 24.99$\times$ and 33.13$\times$ in single core and multicore systems, with a 8.79% area overhead. The Hardware Efficient Approach achieves improvements of 22.47$\times$ and 31.83$\times$, with a 7.23% area overhead. The Primal Approach is capable of preventing endurance attacks and is also compatible with the recently proposed countermeasures for timing channel attacks on LLC.