A ramp-based background calibration technique for timing mismatch in time-interleaved ADCs

This paper presents a ramp-based background calibration technique for timing skew detection and correction in time-interleaved analog-to-digital converters (TI ADCs). The method achieves input independence through an internally generated ramp calibration signal. To enable the calibration to operate in the background without interrupting the ADC’s conversion process, a replica switch is integrated into each sub-ADC to sample the designated ramp signal. The comparator determines the sign of the timing skew by comparing the sampled values of the replica and reference switches. This technique is more efficient than traditional statistical-based algorithms and demonstrates more rapid convergence speed. Furthermore, contrary to algorithms utilizing FIR filters or reference ADCs, the simplified timing skew detection and correction circuit provides lower power consumption and hardware overhead. To validate the proposed technique, it was applied to a 12-bit, 2 GS/s, 4-channel TI ADC. Simulation results demonstrate the feasibility and accuracy of this calibration technique.