基于时域三维步态规划和逆运动学混合信号ZMP步态调度的65nm仿人机器人片上系统

IF 4.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Qiankai Cao;Juin Chuen Oh;Jie Gu
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引用次数: 0

摘要

本文提出了一种仿人机器人的脚步规划芯片。它集成了用于高级三维步态规划的时域图搜索引擎和具有神经逆运动学的混合信号零力矩点(ZMP)步态调度程序,实现了高效的低级运动控制。这项工作的主要贡献包括用于3-D足迹规划的时域图搜索引擎,具有3-D搜索功能,用于实时调整的$D^{\ast} $重新规划,冗余路径阻塞和有效的结果读出。此外,它还引入了一种节能的混合信号ZMP步态调度器来保持机器人的平衡,以及一个基于时域神经网络的逆运动学模块来控制机器人的关节。这项工作在一个使用65纳米片上系统(SoC)的完全组装机器人上进行了现场演示,与之前的工作相比,图搜索节省了2.7倍的能源,运动控制的能源效率提高了18.4倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 65-nm Humanoid Robot System-on-Chip Using Time-Domain 3-D Footstep Planning and Mixed-Signal ZMP Gait Scheduler With Inverse Kinematics
This work presents a footstep planning chip for humanoid robot. It integrates a time-domain graph search engine for high-level 3-D footstep planning and a mixed-signal zero moment point (ZMP) gait scheduler with neural inverse kinematics, enabling efficient low-level motion control. The key contributions of this work include a time-domain graph search engine for 3-D footstep planning, featuring 3-D search capabilities, $D^{\ast } $ replanning for real-time adjustments, redundant path blocking, and efficient result readout. In addition, it introduces an energy-efficient mixed-signal ZMP gait scheduler for maintaining robot balance, along with a time-domain neural-network-based inverse kinematics module for controlling robot joints. This work is demonstrated in situ on a fully assembled robot using the 65-nm system-on-chip (SoC), achieving $2.7\times $ energy savings for graph search and an $18.4\times $ improvement in energy efficiency for motion control compared with prior works.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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