用于大面积和超高带宽高能粒子探测器的跨阻放大器

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jiayi Wang , Yichen Zhang , Yuanjun Guan , Tao Wang , Qianchuan Yi , Wenxin Jiang , Xiaopu Gu , Li Zhang , Binbing Huang , Tianyan Han , Lilei Hu
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引用次数: 0

摘要

在高能粒子探测领域,在实现大的敏感区域和保证探测器的高速响应之间存在权衡。目前的方法,如负米勒电容,在提高检测面积和响应速度方面取得了进展。然而,这些设计经常受到寄生电容的限制,特别是在较大的检测区域,这最终限制了带宽。本研究提出了一种结合优化前端电路的分段集成方法来克服这些挑战。通过将单个大敏感区域分割成更小的像素,每个像素与独立的前端跨阻放大器(TIA)耦合,该设计可以在保持大敏感区域的同时显着提高响应速度。虽然它使整个系统复杂化,但每个像素的输出信号被求和以保持探测器的大面积能力。本研究开发了用于线性和盖革模式的新型前端电路,在检测器增益和带宽方面提供了卓越的性能。在线性模式下,多通道TIA被设计为同时处理多达32个像素,提供50 dBΩ的增益和450 MHz的带宽,尽管寄生电容为160 pF。对于盖革模式,提出了一种具有前馈的新型TIA,为具有5 pF寄生电容的像素提供70 dBΩ和450 MHz带宽,而无需补偿电容器。为了实现快速的单粒子计数,设计了一种四延迟触发采样比较器结构,在工艺限制下采样率达到4 GS/s。该电路采用180nm CMOS工艺设计,并通过Sentaurus和Cadence仿真软件进行验证,检测面积为68.8 mm2,截止频率为450mhz,性能优异。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Transimpedance amplifiers for large-area and ultrahigh bandwidth high-energy particle detectors
In the realm of high-energy particle detection, a trade-off exists between achieving a large sensitive area and ensuring high-speed detector response. Current methodologies, such as negative Miller capacitance, have made progress in enhancing both detection area and response speed. Nevertheless, these designs frequently suffer from limitations in parasitic capacitance, especially with large detection areas, which ultimately constrains bandwidth. This study introduces a segmented-integration method combined with optimized front-end circuits to overcome these challenges. By segmenting a single large sensitive area into smaller pixels, each coupled with an independent front-end transimpedance amplifier (TIA), this design can significantly enhance the response speed while maintaining a large sensitive area. Although it complicates the overall system, the output signals from each pixel are summed to preserve the detector's large-area capability. This study has developed novel front-end circuits for both linear and Geiger modes, offering exceptional performance in terms of detector gain and bandwidth. In linear mode, a multi-channel TIA is designed to handle up to 32 pixels simultaneously, providing a gain of 50 dBΩ and 450 MHz bandwidth despite 160 pF parasitic capacitance. For Geiger mode, a novel TIA with a feedforward is proposed, providing a gain of 70 dBΩ and 450 MHz bandwidth for a pixel with a 5 pF parasitic capacitance without the need for compensating capacitors. To enable rapid single-particle counting, a four-delay trigger sampling comparator structure is designed with a sampling rate reaching 4 GS/s under process limitation. The circuits are designed in 180 nm CMOS process and verified through Sentaurus and Cadence simulation software, demonstrating excellent performance with a 68.8 mm2 detection area and an ultrahigh cutoff frequency of 450 MHz.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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