A simulation optimization method for Verilog-AMS IBIS model under overclocking

The Input/Output Buffer Information Specification (IBIS) model has effectively described the electrical characteristics of circuit input and output ports while safeguarding intellectual property. This model focuses on the analysis of the analog behavior of digital integrated circuits, specifically focusing on the electrical characteristic of I/O buffers, by considering the voltage and current waveforms of the digital I/O signals. However, under overclocking conditions, the model experiences distortion and reduced accuracy due to decreased circuit stability. To address this limitation, we introduce an optimized model designed to resist simulation distortions in the IBIS model during overclocking. First, we defined the relevant variables based on the IBIS circuit and constructed a physical model framework. Next, we studied the monotonicity and sufficient conditions of the physical model, established the relationship between model output and variable parameters, and derived the corresponding IBIS mathematical relationship. Then, to address distortion under overclocking conditions, we adjusted the model variables by setting weighting coefficients tailored to different scenarios, ensuring the output values were closer to the baseline model and significantly enhancing the model's resilience against overclocking distortions. Extensive optimization experiments on three different devices confirm the general applicability of our proposed method, achieving optimization rates exceeding 90 % while maintaining high consistency with the TL baseline model. Notably, our approach improves overclocking simulation accuracy by 21.7 % with only a 2.2 % increase in CPU time, surpassing existing methods. This work addresses the IBIS model's overclocking distortion issue, significantly advancing the accuracy of circuit device simulations.