Phase regulated design strategy of antiferroelectric Cd-modified (Pb, La) (Sn, Zr, Ti) O3 ceramics for pulsed power capacitors

Chip capacitors used in pulsed filed can offer extraordinary discharge energy under elevated electric fields which can be used in high power pulse. However, the low energy density for dielectric ceramic limits the total discharge energy, instead, multilayer-structured design needs to be developed. The ensuing problem is to develop low-temperature sintered ceramics which can be used for the fabrication of multilayered ceramics by cofiring with low-cost Cu electrode. The present study aims to lower sintering temperature and tailors antiferroelectric performances of Cd-doped (Pb, La)(Sn, Zr, Ti)O₃ (PCLSZT) ceramics by phase regulation. The case indicates that the modification of Cd largely reduces the sintering temperature, while Ti regulation can gradually induce an orthorhombic-tetragonal phase transition to optimize dielectric energy storage. The promising energy properties can be obtained (Pb_0.955Cd_0.015La_0.02)(Sn_0.5Zr_0.45Ti_0.05)O₃ under a low field of 260 kV/cm with a charge energy density of 3.52 J/cm³, an energy efficiency of 85%, respectively, accompanied by a rapid discharge speed of t_0.9 = 0.74 μs. This indicates the tunability of energy property in AFE Cd-doped PCLSZT ceramics, thereby providing a potential alternative to develop emerging materials for multilayered pulsed power components.