PINSim:用于模拟智能视觉传感器的处理内传感器和近传感器模拟器

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Sepehr Tabrizchi;Mehrdad Morsali;David Pan;Shaahin Angizi;Arman Roohi
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引用次数: 0

摘要

这封信介绍了PINSim,一个用户友好且灵活的框架,用于在早期设计阶段模拟新兴的智能视觉传感器。PINSim能够实现传感器附近和传感器内部的集成传感和处理,有效地解决数据移动和耗电的模数转换器等挑战。该框架提供了一个灵活的接口和广泛的设计选项,可以使用分层结构定制基于传感器的加速器的效率和精度。它的组织从设备级向上跨越到算法级。PINSim实现了电路级性能指标的指令精确评估。与SPICE模拟相比,PINSim实现了超过25,000倍的加速,平均错误率低于4.1%。此外,它支持多层感知器(MLP)和卷积神经网络(CNN)模型,其局限性取决于物联网预算约束。通过促进各种设计参数的探索和优化,PiNSim使研究人员和工程师能够为广泛的应用开发节能和高性能的智能视觉传感器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors
This letter introduces PINSim, a user-friendly and flexible framework for simulating emerging smart vision sensors in the early design stages. PINSim enables the realization of integrated sensing and processing near and in the sensor, effectively addressing challenges such as data movement and power-hungry analog-to-digital converters. The framework offers a flexible interface and a wide range of design options for customizing the efficiency and accuracy of processing-near/in-sensor-based accelerators using a hierarchical structure. Its organization spans from the device level upward to the algorithm level. PINSim realizes instruction-accurate evaluation of circuit-level performance metrics. PINSim achieves over $25,000\times$ speed-up compared to SPICE simulation with less than a 4.1% error rate on average. Furthermore, it supports both multilayer perceptron (MLP) and convolutional neural network (CNN) models, with limitations determined by IoT budget constraints. By facilitating the exploration and optimization of various design parameters, PiNSim empowers researchers and engineers to develop energy-efficient and high-performance smart vision sensors for a wide range of applications.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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