一个0.4 V， 12.2 pW漏电，36.5 fJ/阶跃开关效率的22nm FDSOI数据保持触发器

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-20 DOI:10.1109/TVLSI.2024.3453946

Yuxin Ji;Yuhang Zhang;Changyan Chen;Jian Zhao;Fakhrul Zaman Rokhani;Yehea Ismail;Yongfu Li

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引用次数: 0

摘要

数据保持触发器（dr - ff）在睡眠模式下有效地维护数据，并在活动模式和睡眠模式之间转换时保持状态。本文提出了一种超低功耗DR-FF设计，该设计具有改进的自主数据保留（ADR）锁存器，在电源电压范围降至接近/亚阈值的情况下工作，实现了12.2 pW的睡眠模式泄漏功率，比以前的CMOS DR-FF低1.4倍至3.8倍。我们提出的dr - ff消耗的最低有源模式切换效率为36.5 fJ/步，比先前的工作低1.2 - 4倍，转换效率为1.9 fJ/步。此外，我们提出的dr - ff需要最小的控制信号、逻辑门和开关，大大降低了设计复杂性，并避免了非易失性数据保留ff （nv - ff）的缺点。

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A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI

Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW,

$1.4\times $

–

$3.8\times $

less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step,

$1.2\times $

–

$4\times $

less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.