基于578 tops /W rram的微型AI边缘设备二进制卷积神经网络宏

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Lixun Wang;Yuejun Zhang;Pengjun Wang;Jianguo Yang;Huihong Zhang;Gang Li;Qikang Li
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引用次数: 0

摘要

这种新型的非易失性内存计算(nvCIM)技术使数据能够就地存储和处理,为边缘人工智能设备中机器学习算法的广泛部署提供了可行的解决方案。然而,当前基于加权电流求和的nvCIM方法在处理高精度模拟信号时面临着设备非理想性和大量时间、存储和能量开销等挑战。为了解决这些问题,我们提出了一种基于电阻随机存取存储器(RRAM)的二进制卷积宏,用于构建完整的二进制卷积神经网络(BCNN)硬件电路,以低权重精度加速边缘人工智能应用。该宏在电路级执行误差补偿,并提供稳定的轨对轨输出,消除了任何adc或处理器执行辅助计算的需要。实验结果表明,本文提出的BCNN全硬件计算系统在CIFAR10 (MNIST)数据集上的片上识别准确率为90.7%(98.64%),与软件识别准确率相比下降0.98%(0.59%)。此外,该二进制卷积宏在136 MHz时实现了320 GOPS的最大吞吐量和578 TOPS/W的峰值能量效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices
The novel nonvolatile computing-in-memory (nvCIM) technology enables data to be stored and processed in situ, providing a feasible solution for the widespread deployment of machine learning algorithms in edge AI devices. However, current nvCIM approaches based on weighted current summation face challenges such as device nonidealities and substantial time, storage, and energy overheads when handling high-precision analog signals. To address these issues, we propose a resistive random access memory (RRAM)-based binary convolution macro for constructing a complete binary convolutional neural network (BCNN) hardware circuit, accelerating edge AI applications with low-weight precision. This macro performs error compensation at the circuit level and provides stable rail-to-rail output, eliminating the need for any ADCs or processor to perform auxiliary computations. Experimental results demonstrate that the proposed BCNN full-hardware computing system achieves on-chip recognition accuracy of 90.7% (98.64%) on the CIFAR10 (MNIST) dataset, which represents a decrease of 0.98% (0.59%) compared to software recognition accuracy. In addition, this binary convolution macro achieves a maximum throughput of 320 GOPS and a peak energy efficiency of 578 TOPS/W at 136 MHz.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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