宽带GaAs数字阶跃衰减器的分析与设计

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-30 DOI:10.1109/TVLSI.2024.3461715

Quanzhen Liang;Xiao Wang;Kuisong Wang;Yuepeng Yan;Xiaoxin Liang

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引用次数: 0

摘要

简要分析了数字阶跃衰减器（dsa）中产生幅度和相位误差的原因，提出了串联电感补偿结构（SICS）和小比特补偿结构两种新型结构来减小这两种误差。提出了一种具有超宽带、低插入损耗和高精度的6位DSA，其面积仅为0.51 mm2，在0.5 dB步长中衰减范围为31.5 dB。测量结果表明，64种衰减状态的均方根（rms）幅度和相位误差分别在0.18 dB和8°以内。插入损耗优于2.54 dB，输入1db压缩点（ip1db）优于29dbm。据我们所知，该芯片采用0.25- $\mu $ m GaAs p-HEMT工艺，在2-22 GHz范围内具有最高的衰减精度，最低的插入损耗，最佳的IP1 dB和良好的匹配性能。

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Analysis and Design of Wideband GaAs Digital Step Attenuators

This brief analyses the causes of amplitude and phase errors in digital step attenuators (DSAs), and proposes two novel structures, namely, the series inductive compensation structure (SICS) and the small-bit compensation structure, to reduce these two kinds of errors. A 6-bit DSA with ultrawideband, low insertion loss, and high accuracy is presented, which has an area of only 0.51 mm2 and shows an attenuation range of 31.5 dB in 0.5 dB steps. Measurements reveal that the root-mean-square (rms) amplitude and phase errors for the 64 attenuation states are within 0.18 dB and 8°, respectively. The insertion loss is better than 2.54 dB, and the input 1 dB compression point (IP1 dB) is better than 29 dBm. To the best of our knowledge, this chip presents the highest attenuation accuracy, the lowest insertion loss, the best IP1 dB, and a good matching performance in the range of 2–22 GHz using the 0.25-

$\mu $

m GaAs p-HEMT process.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.