A real-time, scalable, fast and resource-efficient decoder for a quantum computer

The development of quantum computers will require the careful management of the noise effects associated with qubit performance. However, the decoders responsible for diagnosing noise-induced computational errors must use resources efficiently to enable scaling to large qubit counts and cryogenic operation. They must also operate at speed, to avoid an exponential slowdown in the logical clock rate of the quantum computer. To overcome these challenges, we introduce the Collision Clustering decoder and demonstrate its implementation on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) hardware. We simulate logical memory experiments using the leading quantum error correction scheme (the surface code) and demonstrate megahertz decoding speed—matching the requirements of fast-operating modalities such as superconducting qubits—up to an 881 qubit surface code with the FPGA and 1,057 qubit surface code with the ASIC. The ASIC design occupies 0.06 mm2 and consumes only 8 mW of power. The Collision Clustering decoder is introduced, which requires few logical resources on field-programmable gate array hardware, and low power and area occupation on application-specific integrated circuit hardware, while being performant enough to keep up with the syndrome generation time of a quantum processing unit.