Straw：一种应力感知的基于wl的高密度NAND闪存固态硬盘读回收技术

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-12-12 DOI:10.1109/LCA.2024.3516205

Myoungjun Chun;Jaeyong Lee;Inhyuk Choi;Jisung Park;Myungsuk Kim;Jihong Kim

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引用次数: 0

摘要

虽然读干扰已经成为一个主要的可靠性问题，但在现代NAND闪存中，读干扰的管理还没有得到彻底的研究。通过使用现代NAND闪存的器件特性研究，我们观察到读取页面会对每个WL产生异构可靠性影响，这使得现有的块级读取回收效率极低。我们提出了一种新的WL级读取回收技术，称为Straw，它可以跟踪每个WL上累积的读取干扰效应，并且只回收受严重干扰的WL。通过避免不必要的读回收操作，Straw减少了83.6%由读回收引起的页写，而存储开销可以忽略不计。

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Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs

Although read disturbance has emerged as a major reliability concern, managing read disturbance in modern NAND flash memory has not been thoroughly investigated yet. From a device characterization study using real modern NAND flash memory, we observe that reading a page incurs heterogeneous reliability impacts on each WL, which makes the existing block-level read reclaim extremely inefficient. We propose a new WL-level read-reclaim technique, called Straw , which keeps track of the accumulated read-disturbance effect on each WL and reclaims only heavily-disturbed WLs. By avoiding unnecessary read-reclaim operations, Straw reduces read-reclaim-induced page writes by 83.6% with negligible storage overhead.

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.