{"title":"消除位图压缩矩阵的无效计算","authors":"Chaithanya Krishna Vadlamudi;Bahar Asgari","doi":"10.1109/LCA.2024.3516057","DOIUrl":null,"url":null,"abstract":"The primary computations in several applications, such as deep learning recommendation models, graph neural networks, and scientific computing, involve sparse matrix sparse matrix multiplications (SpMSpM). Unlike standard multiplications, SpMSpMs introduce ineffective computations that can negatively impact performance. While several accelerators have been proposed to execute SpMSpM more efficiently, they often incur additional overhead in identifying the effectual arithmetic computations. To solve this issue, we propose Electra, a novel approach designed to reduce ineffectual computations in bitmap-compressed matrices. Electra achieves this by i) performing logical operations on the bitmap data to know whether the arithmetic computation has a zero or non-zero value, and ii) implementing finer granular scheduling of non-zero elements to arithmetic units. Our evaluations suggest that on average, Electra achieves a speedup of 1.27× over the state-of-the-art SpMSpM accelerator with a small area overhead of 64.92 \n<inline-formula><tex-math>$\\text{mm}^{2}$</tex-math></inline-formula>\n based on 45 nm process.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"24 1","pages":"9-12"},"PeriodicalIF":1.4000,"publicationDate":"2024-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices\",\"authors\":\"Chaithanya Krishna Vadlamudi;Bahar Asgari\",\"doi\":\"10.1109/LCA.2024.3516057\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The primary computations in several applications, such as deep learning recommendation models, graph neural networks, and scientific computing, involve sparse matrix sparse matrix multiplications (SpMSpM). Unlike standard multiplications, SpMSpMs introduce ineffective computations that can negatively impact performance. While several accelerators have been proposed to execute SpMSpM more efficiently, they often incur additional overhead in identifying the effectual arithmetic computations. To solve this issue, we propose Electra, a novel approach designed to reduce ineffectual computations in bitmap-compressed matrices. Electra achieves this by i) performing logical operations on the bitmap data to know whether the arithmetic computation has a zero or non-zero value, and ii) implementing finer granular scheduling of non-zero elements to arithmetic units. Our evaluations suggest that on average, Electra achieves a speedup of 1.27× over the state-of-the-art SpMSpM accelerator with a small area overhead of 64.92 \\n<inline-formula><tex-math>$\\\\text{mm}^{2}$</tex-math></inline-formula>\\n based on 45 nm process.\",\"PeriodicalId\":51248,\"journal\":{\"name\":\"IEEE Computer Architecture Letters\",\"volume\":\"24 1\",\"pages\":\"9-12\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2024-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Computer Architecture Letters\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10795167/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Architecture Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10795167/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices
The primary computations in several applications, such as deep learning recommendation models, graph neural networks, and scientific computing, involve sparse matrix sparse matrix multiplications (SpMSpM). Unlike standard multiplications, SpMSpMs introduce ineffective computations that can negatively impact performance. While several accelerators have been proposed to execute SpMSpM more efficiently, they often incur additional overhead in identifying the effectual arithmetic computations. To solve this issue, we propose Electra, a novel approach designed to reduce ineffectual computations in bitmap-compressed matrices. Electra achieves this by i) performing logical operations on the bitmap data to know whether the arithmetic computation has a zero or non-zero value, and ii) implementing finer granular scheduling of non-zero elements to arithmetic units. Our evaluations suggest that on average, Electra achieves a speedup of 1.27× over the state-of-the-art SpMSpM accelerator with a small area overhead of 64.92
$\text{mm}^{2}$
based on 45 nm process.
期刊介绍:
IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.