基于cam的通用映射单元用于图像/点云融合应用的可扩展BEV感知处理器

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Xiaoyu Feng;Xinyuan Lin;Huazhong Yang;Yongpan Liu;Wenyu Sun
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引用次数: 0

摘要

集成多传感器数据(如图像和点云)以实现信息互补对于自动驾驶等3d感知场景至关重要。近年来,基于鸟瞰图的传感器融合受到越来越多的关注,但巨大的计算开销限制了其在边缘的广泛应用。首先,在BEV融合网络中存在大量不规则的内存访问操作。例如,点云分支中的稀疏卷积(SCONVs)和不规则的BEV平面映射导致显著的内存寻址和映射开销。此外,多传感器融合导致模型尺寸的快速扩展,使得单芯片解决方案难以满足需求且价格昂贵。基于上述挑战,本工作提出了一种图像和点云融合处理器,其中有两个亮点:基于内容可寻址存储器(CAM)的深度融合核心,以加速各种不规则的BEV操作,以及支持灵活互连拓扑的芯片级并行设计。该芯片采用28纳米CMOS技术制造。与现有的图像或点云加速器相比,该芯片在稀疏点云处理方面实现了更高的频率、2倍的面积效率和2.61倍的能量效率。据作者所知,这项工作是基于bev的多模态融合网络的第一个加速器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit
The integration of multi-sensor data like image and point cloud for information complementarity is crucial for 3-D perception scenarios like autonomous driving. Recently, bird’s eye view (BEV)-based sensor fusion is attracting more and more attention but the significant computational overhead constrains their widespread application at the edge. First, there are numerous irregular memory access operations in BEV fusion networks. For example, sparse convolutions (SCONVs) in the point cloud branch and irregular BEV plane mapping result in significant memory addressing and mapping overhead. Furthermore, multi-sensor fusion leads to rapid expansion of model size, making it difficult and expensive for single-chip solutions to meet the demands. Based on the above challenges, this work proposes an image and point cloud fusion processor with two highlights: a content addressable memory (CAM)-based deep fusion core to accelerate a variety of irregular BEV operations and chip-level parallelism design supporting flexible interconnect topology. The proposed chip is fabricated in 28-nm CMOS technology. Compared with existing image or point cloud accelerators, the proposed chip achieves higher frequency, $2\times $ higher area efficiency, and $2.61\times $ higher energy efficiency for sparse point cloud processing. To the best of authors’ knowledge, this work is the first accelerator for BEV-based multi-modal fusion networks.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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