{"title":"具有自主波长稳定的45nm CMOS SOI节能单片集成256gb /s光发射机","authors":"Kaisarbek Omirzakhov;Han Hao;Ali Pirmoradi;Firooz Aflatouni","doi":"10.1109/JSSC.2024.3511673","DOIUrl":null,"url":null,"abstract":"This work presents a monolithically integrated eight-channel optical transmitter in the optical C-band. It supports up to 256 Gb/s aggregate data rate using two-section p-n-capacitive micro-ring modulators (MRMs) integrated together with wavelength stabilization circuit, data generator, and high swing electrical drivers on the same CMOS silicon-on-insulator (SOI) chip. The MRMs have an extinction ratio of >10 dB and a quality factor of about 5000 and can be capacitively tuned over about 400 pm with near-zero power consumption. The energy efficiency of the modulator, including per-channel capacitive wavelength tuning and locking, is 15 fJ/bit at 5-Gb/s/channel and 63 fJ/bit at 32-Gb/s/channel for a bit error rate (BER) <inline-formula> <tex-math>${\\lt } 10{^{-12}}$ </tex-math></inline-formula> and the energy efficiency of the transmitter is 328 fJ/b at 32 Gb/s and 113 fJ/b at 10 Gb/s for a BER <inline-formula> <tex-math>${\\lt }~10{^{-12}}$ </tex-math></inline-formula>. The areal bandwidth density of the modulator unit (including MRMs and the driver electronics) and the core area (including MRMs, drivers, electrical and optical routing, control, and data management electronics) are about 13.25 and 3.3 Tb/s/mm2, respectively. The chip is implemented on a 45 nm CMOS SOI process within a footprint of <inline-formula> <tex-math>$1.2 {\\times } 0.5$ </tex-math></inline-formula> mm.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 7","pages":"2522-2531"},"PeriodicalIF":5.6000,"publicationDate":"2024-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Energy Efficient Monolithically Integrated 256 Gb/s Optical Transmitter With Autonomous Wavelength Stabilization in 45 nm CMOS SOI\",\"authors\":\"Kaisarbek Omirzakhov;Han Hao;Ali Pirmoradi;Firooz Aflatouni\",\"doi\":\"10.1109/JSSC.2024.3511673\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a monolithically integrated eight-channel optical transmitter in the optical C-band. It supports up to 256 Gb/s aggregate data rate using two-section p-n-capacitive micro-ring modulators (MRMs) integrated together with wavelength stabilization circuit, data generator, and high swing electrical drivers on the same CMOS silicon-on-insulator (SOI) chip. The MRMs have an extinction ratio of >10 dB and a quality factor of about 5000 and can be capacitively tuned over about 400 pm with near-zero power consumption. The energy efficiency of the modulator, including per-channel capacitive wavelength tuning and locking, is 15 fJ/bit at 5-Gb/s/channel and 63 fJ/bit at 32-Gb/s/channel for a bit error rate (BER) <inline-formula> <tex-math>${\\\\lt } 10{^{-12}}$ </tex-math></inline-formula> and the energy efficiency of the transmitter is 328 fJ/b at 32 Gb/s and 113 fJ/b at 10 Gb/s for a BER <inline-formula> <tex-math>${\\\\lt }~10{^{-12}}$ </tex-math></inline-formula>. The areal bandwidth density of the modulator unit (including MRMs and the driver electronics) and the core area (including MRMs, drivers, electrical and optical routing, control, and data management electronics) are about 13.25 and 3.3 Tb/s/mm2, respectively. The chip is implemented on a 45 nm CMOS SOI process within a footprint of <inline-formula> <tex-math>$1.2 {\\\\times } 0.5$ </tex-math></inline-formula> mm.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"60 7\",\"pages\":\"2522-2531\"},\"PeriodicalIF\":5.6000,\"publicationDate\":\"2024-12-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10804633/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10804633/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Energy Efficient Monolithically Integrated 256 Gb/s Optical Transmitter With Autonomous Wavelength Stabilization in 45 nm CMOS SOI
This work presents a monolithically integrated eight-channel optical transmitter in the optical C-band. It supports up to 256 Gb/s aggregate data rate using two-section p-n-capacitive micro-ring modulators (MRMs) integrated together with wavelength stabilization circuit, data generator, and high swing electrical drivers on the same CMOS silicon-on-insulator (SOI) chip. The MRMs have an extinction ratio of >10 dB and a quality factor of about 5000 and can be capacitively tuned over about 400 pm with near-zero power consumption. The energy efficiency of the modulator, including per-channel capacitive wavelength tuning and locking, is 15 fJ/bit at 5-Gb/s/channel and 63 fJ/bit at 32-Gb/s/channel for a bit error rate (BER) ${\lt } 10{^{-12}}$ and the energy efficiency of the transmitter is 328 fJ/b at 32 Gb/s and 113 fJ/b at 10 Gb/s for a BER ${\lt }~10{^{-12}}$ . The areal bandwidth density of the modulator unit (including MRMs and the driver electronics) and the core area (including MRMs, drivers, electrical and optical routing, control, and data management electronics) are about 13.25 and 3.3 Tb/s/mm2, respectively. The chip is implemented on a 45 nm CMOS SOI process within a footprint of $1.2 {\times } 0.5$ mm.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.