ZoneBuffer:适用于 ZNS 固态硬盘的高效缓冲区管理方案

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Hongtao Wang;Peiquan Jin
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引用次数: 0

摘要

分区命名空间ssd (ZNS ssd)的引入对现有的缓冲区管理方案提出了新的挑战。除了读写不对称和有限的写入持久性等传统SSD特性外,ZNS SSD还具有独特的约束,例如要求在每个区域内进行顺序写入。这些特性使得传统的缓冲策略与ZNS ssd不兼容。本文介绍了ZoneBuffer,一种专为ZNS固态硬盘设计的新型缓冲方案。ZoneBuffer的创新在于两个关键方面。首先,它引入了一个新的缓冲区结构,包括一个工作区和一个优先级区域。优先级区域进一步划分为干净页面队列和脏页面区域集群。通过将缓冲区替换限制在优先级区域,ZoneBuffer确保了ZNS ssd的优化。其次,ZoneBuffer结合了一个基于生命周期的聚类算法,将脏页分组在优先级区域内,优化写操作。在真实的ZNS固态硬盘上进行的初步实验证明了ZoneBuffer的有效性。与LRU和CFLRU等传统方案相比,ZoneBuffer的性能得到了显著提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs
The introduction of Zoned Namespace SSDs (ZNS SSDs) presents new challenges for existing buffer management schemes. In addition to traditional SSD characteristics such as read/write asymmetry and limited write endurance, ZNS SSDs possess unique constraints, such as requiring sequential writes within each zone. These features make conventional buffering policies incompatible with ZNS SSDs. This paper introduces ZoneBuffer, a novel buffering scheme designed specifically for ZNS SSDs. ZoneBuffer's innovation lies in two key aspects. First, it introduces a new buffer structure comprising a Work Region and a Priority Region. The Priority Region is further divided into a clean page queue and a zone cluster of dirty pages. By confining buffer replacement to the Priority Region, ZoneBuffer ensures optimization for ZNS SSDs. Second, ZoneBuffer incorporates a lifetime-based clustering algorithm to group dirty pages within the Priority Region, optimizing write operations. Preliminary experiments conducted on a real ZNS SSD demonstrate the effectiveness of ZoneBuffer. Compared with conventional schemes like LRU and CFLRU, the results indicate that ZoneBuffer significantly improves performance.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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