SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication

Polynomial multiplication is a key component in many post-quantum cryptography and homomorphic encryption schemes. One recurring variation, ternary polynomial multiplication over ring $\mathbb {Z}_{q}/(x^{n}+1)$ where one input polynomial has ternary coefficients {−1,0,1} and the other has large integer coefficients {0, $q-1$ }, has recently drawn significant attention from various communities. Following this trend, this paper presents a novel SCAL able and area- E fficient S ystolic (SCALES) accelerator for ternary polynomial multiplication. In total, we have carried out three layers of coherent interdependent efforts. First, we have rigorously derived a novel block-processing strategy and algorithm based on the schoolbook method for polynomial multiplication. Then, we have innovatively implemented the proposed algorithm as the SCALES accelerator with the help of a number of field-programmable gate array (FPGA)-oriented optimization techniques. Lastly, we have conducted a thorough implementation analysis to showcase the efficiency of the proposed accelerator. The comparison demonstrated that the SCALES accelerator has at least 19.0% and 23.8% less equivalent area-time product (eATP) than the state-of-the-art designs. We hope this work can stimulate continued research in the field.