Phuoc B. T. Huynh;Gyeong-Seok Lee;Jun-Young Park;Tae-Yeoul Yun
{"title":"基于电流复用的低功率LNA电感负载同步噪声与输入匹配技术","authors":"Phuoc B. T. Huynh;Gyeong-Seok Lee;Jun-Young Park;Tae-Yeoul Yun","doi":"10.1109/JSSC.2024.3511578","DOIUrl":null,"url":null,"abstract":"This article presents an inductive loading simultaneous noise and input matching (ILSNIM) technique for a low-power low-noise amplifier (LNA). In contrast to conventional simultaneous noise and input matching (SNIM) methods, where lossy resistance associated with an on-chip low-Q gate inductor substantially degrades the total noise figure (NF) performance, the input stage of the proposed LNA exploits the gate-drain capacitance feedback incorporated with inductive loading for the first time to construct the input impedance network. This design approach overcomes the NF limitation in conventional SNIM techniques by eliminating the lossy gate inductor while boosting the transconductance to achieve SNIM under low power consumption. Furthermore, a current-reuse structure with a cascaded stage is applied not only to enhance the overall gain but also to generate a noiseless resistive component that addresses the instability issue without adverse impacts on other performances. Fabricated using a 0.11-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m complementary metal-oxide-semiconductor (CMOS) process, the proposed ILSNIM LNA demonstrates a gain of 13.6 dB, an NF of 2.8 dB, and a third-order input intercept point (IIP3) of -5.2 dBm at 6.8 GHz under a 1.2-mW power dissipation from a 1-V supply.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 7","pages":"2461-2472"},"PeriodicalIF":5.6000,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Inductive Loading Simultaneous Noise and Input Matching Technique With Current Reuse for Low-Power LNA\",\"authors\":\"Phuoc B. T. Huynh;Gyeong-Seok Lee;Jun-Young Park;Tae-Yeoul Yun\",\"doi\":\"10.1109/JSSC.2024.3511578\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents an inductive loading simultaneous noise and input matching (ILSNIM) technique for a low-power low-noise amplifier (LNA). In contrast to conventional simultaneous noise and input matching (SNIM) methods, where lossy resistance associated with an on-chip low-Q gate inductor substantially degrades the total noise figure (NF) performance, the input stage of the proposed LNA exploits the gate-drain capacitance feedback incorporated with inductive loading for the first time to construct the input impedance network. This design approach overcomes the NF limitation in conventional SNIM techniques by eliminating the lossy gate inductor while boosting the transconductance to achieve SNIM under low power consumption. Furthermore, a current-reuse structure with a cascaded stage is applied not only to enhance the overall gain but also to generate a noiseless resistive component that addresses the instability issue without adverse impacts on other performances. Fabricated using a 0.11-<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m complementary metal-oxide-semiconductor (CMOS) process, the proposed ILSNIM LNA demonstrates a gain of 13.6 dB, an NF of 2.8 dB, and a third-order input intercept point (IIP3) of -5.2 dBm at 6.8 GHz under a 1.2-mW power dissipation from a 1-V supply.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"60 7\",\"pages\":\"2461-2472\"},\"PeriodicalIF\":5.6000,\"publicationDate\":\"2024-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10787398/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10787398/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
An Inductive Loading Simultaneous Noise and Input Matching Technique With Current Reuse for Low-Power LNA
This article presents an inductive loading simultaneous noise and input matching (ILSNIM) technique for a low-power low-noise amplifier (LNA). In contrast to conventional simultaneous noise and input matching (SNIM) methods, where lossy resistance associated with an on-chip low-Q gate inductor substantially degrades the total noise figure (NF) performance, the input stage of the proposed LNA exploits the gate-drain capacitance feedback incorporated with inductive loading for the first time to construct the input impedance network. This design approach overcomes the NF limitation in conventional SNIM techniques by eliminating the lossy gate inductor while boosting the transconductance to achieve SNIM under low power consumption. Furthermore, a current-reuse structure with a cascaded stage is applied not only to enhance the overall gain but also to generate a noiseless resistive component that addresses the instability issue without adverse impacts on other performances. Fabricated using a 0.11-$\mu $ m complementary metal-oxide-semiconductor (CMOS) process, the proposed ILSNIM LNA demonstrates a gain of 13.6 dB, an NF of 2.8 dB, and a third-order input intercept point (IIP3) of -5.2 dBm at 6.8 GHz under a 1.2-mW power dissipation from a 1-V supply.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.