一种用于植入式医疗设备的具有动态电压供应的高压兼容86%峰值效率电流模式刺激器

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
You You;Ruizhi Tian;Yacong Zhang;Zhongjian Chen;Wengao Lu;Yihan Zhang
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引用次数: 0

摘要

本文介绍了一种符合高压(HV)标准的节能电流模式刺激器,该刺激器具有基于升压的动态电压供应(DVS),以最大限度地减少电压差。刺激器采用按需激活异步策略,指示升压转换器产生跟踪电极电压降的动态增加的高电压,从而实现近绝热刺激。该策略依赖于测量升压的变电压转换比(VCR),本文提出了一个8位电压比量化器(VRQ)。此外,升压变换器采用低功率,快速度,高压栅极驱动器(HVGD)来控制其p型功率开关,该开关将电感器连接到高压输出。本文还介绍了一种用于控制n型电源开关和HVGD的脉冲信号的专用数字电路。这个数字电路是由一个电流匮乏的环形振荡器的五相时钟驱动的。环形振荡器的输出采用了一种高效的旋转对称电平移位器,可以平移其电平并改善其上升/下降时间。升压变换器达到90.2%的峰值效率,使刺激器在6 mA的双相刺激期间实现高达86%的端到端能量效率。采用0.18- $\boldsymbol {\mu}\mathbf {m}$双极cmos - dmos (BCD)技术制作的刺激器集成电路占地面积仅为2.16 mm2。它具有低静态功耗,为$1.78~\boldsymbol {\mu}\mathbf {W}$,具有延长使用寿命和减小外形因素的电池供电植入物。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A High-Voltage-Compliant 86% Peak Efficiency Current-Mode Stimulator With Dynamic Voltage Supply for Implantable Medical Devices
This article introduces a high-voltage (HV) compliant, energy-efficient current-mode stimulator featuring a proposed boost-based dynamic voltage supply (DVS) to minimize the voltage dropout. The stimulator employs an activate-on-demand asynchronous strategy, instructing the boost converter to generate the dynamically increased high voltage that tracks the electrode’s voltage drop, thus achieving a near-adiabatic stimulation. The strategy relies on measuring the boost’s varying voltage conversion ratio (VCR), which is facilitated by an 8-bit voltage ratio quantizer (VRQ) proposed in this article. Furthermore, the boost converter employs a low-power, fast-speed, HV gate driver (HVGD) to control its p-type power switch that connects the inductor to the HV output. This article also presents a dedicated digital circuit that generates the pulse signals for controlling the n-type power switch and the HVGD. This digital circuit is driven by a five-phase clock from a current-starved ring oscillator. A highly efficient rotationally symmetric level shifter is utilized for the ring oscillator’s output, translating its level and improving its rise/fall time. The boost converter reaches a peak efficiency of 90.2%, enabling the stimulator to achieve an end-to-end energy efficiency of up to 86% during a biphasic stimulation of 6 mA. The stimulator IC, fabricated using 0.18- $\boldsymbol {\mu }\mathbf {m}$ bipolar-CMOS–DMOS (BCD) technology, occupies a compact area of 2.16 mm2. It exhibits low static power consumption at $1.78~\boldsymbol {\mu }\mathbf {W}$ , promising battery-powered implants with an extended lifetime and a reduced form factor.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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